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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ITS, WBS, RCC | 2023-12-22 14:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
Optimization of commute planning by CMOS annealing for traffic congestion mitigation Kento Hasegawa, Yusuke Sugita (Hitachi), Katsuhiko Mutsuga (AISIN), Toshiharu Ieki (AISIN SOFTWARE), Masanao Yamaoka (Hitachi)  WBS2023-60 ITS2023-43 RCC2023-54 |
Traffic congestion is one of the serious social issues in terms of economic loss and environmental impact, and various c... [more] | WBS2023-60 ITS2023-43 RCC2023-54 pp.167-172 |
| SDM, ICD, ITE-IST [detail] | 2021-08-17 11:00 |
Online | Online | [Invited Talk]
Development of 144-bit CMOS Annealing Processor with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Mashiro Mayumi, Masanao Yamaoka (Hitachi) SDM2021-31 ICD2021-2 |
[more] | SDM2021-31 ICD2021-2 pp.7-11 |
| SDM, ICD, ITE-IST [detail] | 2019-08-07 13:30 |
Hokkaido | Hokkaido Univ., Graduate School /Faculty of Information Science and | [Invited Talk]
A Scalable CMOS Annealing Processor for Solving Large-scale Combinatorial Optimization Problems Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka (Hitachi) SDM2019-36 ICD2019-1 |
This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The ... [more] | SDM2019-36 ICD2019-1 pp.1-5 |
| SDM, ICD, ITE-IST [detail] | 2018-08-08 13:40 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | [Invited Talk]
CMOS Annealing Machine for Combinatorial Optimization Problems Masanao Yamaoka (Hitachi) SDM2018-41 ICD2018-28 |
(To be available after the conference date) [more] | SDM2018-41 ICD2018-28 p.89 |
| CAS, SIP, MSS, VLD | 2018-06-15 15:45 |
Hokkaido | Hokkaido Univ. (Frontier Research in Applied Sciences Build.) | * Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka (Waseda Univ.), Masato Hayashi, Masanao Yamaoka (Ltd), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2018-31 VLD2018-34 SIP2018-51 MSS2018-31 |
(To be available after the conference date) [more] | CAS2018-31 VLD2018-34 SIP2018-51 MSS2018-31 pp.161-166 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-23 15:10 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | CPSY2017-4 DC2017-4 RECONF2017-21 |
A CMOS Ising Computing based on Ising model, which effectively solves combinational optimization problems necessary for ... [more] | CPSY2017-4 DC2017-4 RECONF2017-21 pp.15-20(CPSY), pp.15-20(DC), pp.111-116(RECONF) |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 14:40 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | [Keynote Address]
CMOS Annealing Machine to Solve Combinatorial Optimization Problems for IoT Era Masanao Yamaoka (Hitachi) VLD2016-59 CPM2016-81 ICD2016-42 IE2016-76 CPSY2016-52 DC2016-53 RECONF2016-49 |
A new computing machine, CMOS annealing machine, using Ising model that effectively solves combinatorial optimization pr... [more] | VLD2016-59 CPM2016-81 ICD2016-42 IE2016-76 CPSY2016-52 DC2016-53 RECONF2016-49 pp.91-96(VLD), pp.25-30(CPM), pp.25-30(ICD), pp.25-30(IE), pp.27-32(CPSY), pp.91-96(DC), pp.49-54(RECONF) |
| COMP, IPSJ-AL | 2016-06-25 13:40 |
Ishikawa | Contractive graph-minor embedding for CMOS Ising computer Takuya Okuyama, Chihiro Yoshimura, Masato Hayashi, Saki Tanaka, Masanao Yamaoka (Hitachi) COMP2016-11 |
We proposed CMOS Ising computer, which maps the combinatorial optimization problems to the ground state search of Ising ... [more] | COMP2016-11 pp.97-103 |
|
| ICD | 2015-04-17 14:55 |
Nagano | [Invited Talk]
An 1800-Times-Higher Power-Efficient 20k-spin Ising Chip for Combinatorial Optimization Problem with CMOS Annealing Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno (Hitachi) ICD2015-13 |
A new computing architecture using Ising model that effectively solves combinatorial optimization problems is proposed, ... [more] | ICD2015-13 pp.63-68 |
|
| ICD | 2010-04-22 11:15 |
Kanagawa | Shonan Institute of Tech. | A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation Shigenobu Komatsu, Masanao Yamaoka (HITACHI), Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki (Renesas Technology Corp.), Kenichi Osada (HITACHI) ICD2010-4 |
A multi-stage replica bitline scheme for reducing access time by suppressing enable timing variation of a sense amplifie... [more] | ICD2010-4 pp.17-21 |
| ICD | 2009-04-13 15:40 |
Miyagi | Daikanso (Matsushima, Miyagi) | [Panel Discussion]
Which memory technology win win the low-VDD race in SoC? Hideto Hidaka (Renesas Tech.), Masanao Yamaoka (Hitachi, Ltd.), Shinji Miyano (Toshiba Corp.), Satoru Akiyama (Hitachi, Ltd.), Tadahiko Sugibayashi (NEC), Syoichiro Kawashima (Fujitsu Limited), Masataka Osaka (Panasonic) ICD2009-4 |
A panel discussion session will high-light low-voltage memory trends, limitations, and future prospects by discussing on... [more] | ICD2009-4 p.19 |
| ICD | 2008-04-17 10:15 |
Tokyo | [Invited Talk]
65nm Low-Power High-Density SRAM Operable at 1.0V under 3sigma Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda, Yasuhisa Shimazaki (Renesas), Kenichi Osada (Hitachi, Ltd.) ICD2008-2 |
A 1Mb SRAM is fabricated in 65nm LP process with 0.51μm2 cell. An NMOS and PMOS separately applied body bias technique a... [more] | ICD2008-2 pp.7-12 |
|
| ICD | 2006-04-14 13:00 |
Oita | Oita University | [Special Invited Talk]
Low-Power Low-Voltage SRAM Design for Battery Operation Masanao Yamaoka (Hitachi, Ltd.) |
In the processors for mobile devices, the power consumption of the embedded SRAMs has large impact on the total power c... [more] |
ICD2006-17 pp.91-96 |
| ICD, SDM | 2005-08-18 16:20 |
Hokkaido | HAKODATE KOKUSAI HOTEL | SOI; the Trump Card of SOCs in Sub. 50-nm Era
-- Techniques that SOI Conquers Bulk! -- Tadayoshi Enomoto (Chuo Univ.), Takakuni Douseki (NTT), Kazutami Arimoto (Renesas), Jiroh Ida (Oki), Takashi Ipposhi (Renesas), Kazuhiko Miki (Toshiba), Masanao Yamaoka (Hitachi), Makoto Yoshimi (SOITEC) |
(Advance abstract in Japanese is available) [more] | SDM2005-142 ICD2005-81 pp.85-90 |
| ICD | 2005-04-14 09:30 |
Fukuoka | Low-Power Embedded SRAM Modules with Expanded Margins for Writing Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) |
The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SR... [more] | ICD2005-2 pp.7-12 |
|
| ICD | 2004-12-16 10:00 |
Hiroshima | Dynamic-Vth, Dual-Power-Supply SRAM Cell Using D2G-SOI for Low-Power SoC Application Masanao Yamaoka, Kenichi Osada, Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara (Hitachi, Ltd.) |
We developped two SRAM memory cells suitable for low-power SoC. The memory cells are composed of new FD-SOI transistors,... [more] | ICD2004-183 pp.1-5 |
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