IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 1 of 1  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SIS 2010-12-02
15:15
Nara   Circuit Design of a 128-point FFT Processor Using Pipeline MDC Architecture for 8x8 MIMO-OFDM Receivers
Atsushi Orikasa, Yoshikazu Miyanaga, Shingo Yoshizawa (Hokkaido Univ.) SIS2010-45
This report presents a VLSI architecture of 128-point FFT in a 8x8 MIMO-OFDM receiver. A pipeline FFT processor based on... [more] SIS2010-45
pp.59-64
 Results 1 - 1 of 1  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan