Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPSY, DC, IPSJ-ARC [detail] |
2023-08-04 11:45 |
Hokkaido |
Hakodate Arena (Primary: On-site, Secondary: Online) |
CPSY2023-19 DC2023-19 |
(To be available after the conference date) [more] |
CPSY2023-19 DC2023-19 pp.67-71 |
CPSY, DC, IPSJ-ARC [detail] |
2022-07-29 09:45 |
Yamaguchi |
Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
CPSY2022-13 DC2022-13 |
(To be available after the conference date) [more] |
CPSY2022-13 DC2022-13 pp.71-76 |
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] |
2022-01-25 11:50 |
Online |
Online |
VLD2021-67 CPSY2021-36 RECONF2021-75 |
(To be available after the conference date) [more] |
VLD2021-67 CPSY2021-36 RECONF2021-75 pp.102-107 |
DC, CPSY, IPSJ-ARC [detail] |
2021-10-11 13:00 |
Online |
Online |
CPSY2021-13 DC2021-13 |
(To be available after the conference date) [more] |
CPSY2021-13 DC2021-13 pp.7-12 |
CPSY, DC, IPSJ-ARC [detail] |
2021-07-20 16:15 |
Online |
Online |
CPSY2021-5 DC2021-5 |
(To be available after the conference date) [more] |
CPSY2021-5 DC2021-5 pp.25-30 |
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] |
2021-01-25 09:00 |
Online |
Online |
VLD2020-39 CPSY2020-22 RECONF2020-58 |
(To be available after the conference date) [more] |
VLD2020-39 CPSY2020-22 RECONF2020-58 pp.1-6 |
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] |
2021-01-25 09:50 |
Online |
Online |
Study on Design and Evaluation of Stream Processing Hardware for Sound Simulation by FDTD method Hiroki Tada (JAIST), Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano (R-CCS), Ryuta Kawano, Yasushi Inoguchi (JAIST) VLD2020-41 CPSY2020-24 RECONF2020-60 |
(To be available after the conference date) [more] |
VLD2020-41 CPSY2020-24 RECONF2020-60 pp.13-18 |
CPSY, DC, IPSJ-ARC [detail] |
2020-07-30 15:15 |
Online |
Online |
CPSY2020-3 DC2020-3 |
(To be available after the conference date) [more] |
CPSY2020-3 DC2020-3 pp.15-21 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2020-02-27 14:50 |
Kagoshima |
Yoron-cho Chuou-Kouminkan |
Low-Latency Memory Packet Network Using Bypassing Yoshiya Shikama, Ryuta Kawano, Akram Ben Ahmed, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2019-93 DC2019-99 |
(To be available after the conference date) [more] |
CPSY2019-93 DC2019-99 pp.7-12 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2020-01-22 13:55 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
VLD2019-58 CPSY2019-56 RECONF2019-48 |
(To be available after the conference date) [more] |
VLD2019-58 CPSY2019-56 RECONF2019-48 pp.25-30 |
CPSY, DC, IPSJ-ARC [detail] |
2019-07-25 15:35 |
Hokkaido |
Kitami Civic Hall |
CPSY2019-28 DC2019-28 |
(To be available after the conference date) [more] |
CPSY2019-28 DC2019-28 pp.147-152 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-07 09:00 |
Hiroshima |
Satellite Campus Hiroshima |
A Scalable Multi-Path Selection Method for High-Throughput Interconnection Networks Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2018-38 |
(To be available after the conference date) [more] |
CPSY2018-38 pp.11-16 |
CPSY, DC, IPSJ-ARC (Joint) [detail] |
2018-07-31 16:15 |
Kumamoto |
Kumamoto City International Center |
Measuring and Understanding Throughput of Routing Algorithms Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2018-23 |
(To be available after the conference date) [more] |
CPSY2018-23 pp.133-138 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 09:00 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
CPSY2017-44 |
The number of computing nodes increases for both on-chip multi-core systems and supercomputers. Therefore, the network l... [more] |
CPSY2017-44 pp.23-28 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2016-03-25 09:55 |
Nagasaki |
Fukue Bunka Hall/Rodou Fukushi Center |
An Effective Virtual Channel Allocation Method for Deterministic Deadlock-free Routing Ryuta Kawano, Hiroshi Nakahara (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2015-148 DC2015-102 |
Distributed routing methods with small routing tables are scalable design on irregular networks for large-scale High Per... [more] |
CPSY2015-148 DC2015-102 pp.163-168 |
ICD, CPSY |
2015-12-18 14:30 |
Kyoto |
Kyoto Institute of Technology |
A Low Latency Distributed Routing Method for Random Topologies in HPC Networks Ryuta Kawano, Hiroshi Nakahara (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) ICD2015-90 CPSY2015-103 |
End-to-end network latency has become an important issue for parallel application on large-scale High Performance Comput... [more] |
ICD2015-90 CPSY2015-103 pp.105-110 |
ICD, CPSY |
2015-12-18 14:55 |
Kyoto |
Kyoto Institute of Technology |
Topology Optimization of 3D-Stacked Chips under Maxiumum Wire Length Constraint Hiroshi Nakahara, Daichi Fujiki, Seiichi Tade, Ryota Yasudo, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Koji Nakano (Hiroshima Univ.), Hideharu Amano (Keio Univ.) ICD2015-91 CPSY2015-104 |
(To be available after the conference date) [more] |
ICD2015-91 CPSY2015-104 pp.111-116 |
CPSY, DC (Joint) |
2014-07-29 10:45 |
Niigata |
Toki Messe, Niigata |
Interconnect Design for Low Latency, High Topological Embeddability and Partitioning Capability by Supplementary Optical Circuit Switches Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2014-20 |
This paper focuses on how to efficiently run multiple small parallel applications in a single High-performance computing... [more] |
CPSY2014-20 pp.61-66 |
CPSY, DC (Joint) |
2014-07-29 11:35 |
Niigata |
Toki Messe, Niigata |
Alterable uniform and random NoC through rewiring Seiichi Tade, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2014-22 |
Recently, the number of cores inside a chip has been increased. Network-on-Chip(NoC) is widely utilized for communicatio... [more] |
CPSY2014-22 pp.73-78 |
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] |
2014-03-16 10:50 |
Okinawa |
|
HPC interconnect for high topological embeddability by supplementary optical circuit switches Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2013-111 DC2013-98 |
Our goal is to run multiple parallel applications that have various communication patterns among participating processes... [more] |
CPSY2013-111 DC2013-98 pp.253-258 |