Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD, CPSY, CAS |
2017-12-14 09:50 |
Okinawa |
Art Hotel Ishigakijima |
Design of Quick-Lock Reference-Clock-Less All-Digital CDR using Delay Tunable Buffer for Lock Range Extension Meikan Chin, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) CAS2017-64 ICD2017-52 CPSY2017-61 |
A quick-lock reference-clock-less all-digital burst-mode CDR is proposed. Since the proposed CDR resumes from a standby ... [more] |
CAS2017-64 ICD2017-52 CPSY2017-61 pp.3-8 |
ICD, CPSY, CAS |
2017-12-14 10:10 |
Okinawa |
Art Hotel Ishigakijima |
Design of Non-Binary SAR ADC with Noise-Tunable Comparator Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (The Univ. of Tokyo) CAS2017-65 ICD2017-53 CPSY2017-62 |
A 16-bit non-binary SAR ADC with a noise-tunable comparator for low power consumption is presented. A non-binary-weight... [more] |
CAS2017-65 ICD2017-53 CPSY2017-62 pp.9-13 |
ICD, CPSY, CAS |
2017-12-14 10:40 |
Okinawa |
Art Hotel Ishigakijima |
Performance Analysis of Level-Cross Detection Method based on Stochastic Comparator Taiki Sugiyama, Tetsuya Iizuka (Univ. of Tokyo), Takahiro Yamaguchi (Advantest), Toru Nakura, Kunihiro Asada (Univ. of Tokyo) CAS2017-66 ICD2017-54 CPSY2017-63 |
ADC based on level-cross detection quantizes time rather than voltage. When the clock frequency is doubled, SNR of ADC i... [more] |
CAS2017-66 ICD2017-54 CPSY2017-63 pp.15-20 |
ICD, CPSY |
2015-12-18 15:55 |
Kyoto |
Kyoto Institute of Technology |
Performance Analysis of Analog to Digital Converter Based on Stochastic Comparator Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Tokyo University) ICD2015-93 CPSY2015-106 |
A performance model for Analog to Digital Converter (ADC) based on stochastic comparator has been proposed by analyzing ... [more] |
ICD2015-93 CPSY2015-106 pp.123-128 |
ICD, CPSY |
2015-12-18 16:20 |
Kyoto |
Kyoto Institute of Technology |
A Time-Mode Analog Signal Accumulator Using a Single Buffer Ring without Output Drift Calibration Tomohiko Yano, Toru Nakura, Testuya Iizuka, Kunihiro Asada (Univ. of Tokyo) ICD2015-94 CPSY2015-107 |
This paper presents a time-mode analog signal accumulator whose input and output are both represented by the time differ... [more] |
ICD2015-94 CPSY2015-107 pp.129-134 |
ICD, CPSY |
2015-12-18 16:45 |
Kyoto |
Kyoto Institute of Technology |
Autonomously Tracking PVT Variations of Pulse Width Controlled PLL using Hill-Climbing Method Toi Takashi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada (Tokyo Univ.) ICD2015-95 CPSY2015-108 |
[more] |
ICD2015-95 CPSY2015-108 pp.135-140 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:10 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique Norihito Tohge, Tetsuya Iizuka, Toru Nakura (Univ. of Tokyo), Satoshi Miura, Yoshimichi Murakami (THine), Kunihiro Asada (Univ. of Tokyo) CPM2015-130 ICD2015-55 |
A quick-lock all-digital Clock-Data Recovery circuit that does not require a reference clock is propposed. Internal
Tim... [more] |
CPM2015-130 ICD2015-55 pp.17-22 |
ICD, IE, VLD, IPSJ-SLDM [detail] |
2015-10-26 15:00 |
Miyagi |
|
Design of Fine-Resolution Pulse Shrinking Time-to-Digital Converter Takehisa Koga, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) VLD2015-29 ICD2015-42 IE2015-64 |
A pulse-shrinking Time-to-Digital Converter (TDC) with an offset pulse width detection scheme is presented. In the conve... [more] |
VLD2015-29 ICD2015-42 IE2015-64 pp.13-18 |
ICD, CPSY |
2014-12-02 16:05 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
An accelerating method of NBTI degradation transition analysis based on logic simulation Kazunori Mori, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada (UTokyo) ICD2014-109 CPSY2014-121 |
Negative Bias Temperature Instability (NBTI) degradation is one of the important problems in nano-scale transistors.In t... [more] |
ICD2014-109 CPSY2014-121 pp.141-145 |
ICD, ITE-IST |
2011-07-22 09:25 |
Hiroshima |
Hiroshima Institute of Technology |
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator Tetsuya Iizuka, Kunihiro Asada (Univ. of Tokyo) ICD2011-26 |
This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring o... [more] |
ICD2011-26 pp.63-68 |
ICD, ITE-IST |
2011-07-22 09:50 |
Hiroshima |
Hiroshima Institute of Technology |
On-Chip Resonant Supply Noise Reduction Using Active Decoupling Capacitors Jinmyoung Kim (Tokyo Univ.), Toru Nakura (VDEC), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (VDEC) ICD2011-27 |
[more] |
ICD2011-27 pp.69-72 |
VLD |
2010-09-27 16:30 |
Kyoto |
Kyoto Institute of Technology |
[Invited Talk]
An Automatic Test Generation Framework for Digitally-Assisted Analog Circuit Satoshi Komatsu, Mohamed Abbas (Univ. of Tokyo), Yasuo Furukawa (Advantest), Kunihiro Asada (Univ. of Tokyo) VLD2010-46 |
This paper presents a new analog ATPG (AATPG) framework that generates near-optimal test stimulus for the digitally-assi... [more] |
VLD2010-46 pp.25-30 |
ICD, SDM |
2010-08-26 09:10 |
Hokkaido |
Sapporo Center for Gender Equality |
On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) SDM2010-124 ICD2010-39 |
This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitanc... [more] |
SDM2010-124 ICD2010-39 pp.1-4 |
ICD, ITE-IST |
2010-07-22 10:45 |
Osaka |
Josho Gakuen Osaka Center |
Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) ICD2010-24 |
In this paper, we propose an all-digital process variability monitor which utilizes a simple buffer ring with a pulse co... [more] |
ICD2010-24 pp.15-20 |
ICD, ITE-IST |
2009-10-02 09:10 |
Tokyo |
CIC Tokyo (Tamachi) |
Study of Active Substrate Noise Cancelling Technique using PowerLine di/dt Detector Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) ICD2009-46 |
This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time diff... [more] |
ICD2009-46 pp.69-73 |
VLD, ICD |
2008-03-07 10:05 |
Okinawa |
TiRuRu |
A Self-timed Processor with Dynamic Voltage Scaling Taku Sogabe, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) VLD2007-158 ICD2007-181 |
As PVT variations get larger, synchronous circuits are getting less reliable and timing margins are getting larger. Self... [more] |
VLD2007-158 ICD2007-181 pp.13-18 |
CPM, ICD |
2008-01-17 10:05 |
Tokyo |
Kikai-Shinko-Kaikan Bldg |
ptimization of Active Substrate Noise Cancellng Technique Using Multi di/dt Detectors Toru Nakura, Taisuke Kazama, Makoto Ikeda, Kunihiro Asada (The Univ. of Tokyo) CPM2007-130 ICD2007-141 |
This paper demonstrates study on a feedforward active substrate noise cancelling technique using a power supply di/dt de... [more] |
CPM2007-130 ICD2007-141 pp.11-16 |
ICD, ITE-IST |
2007-07-27 10:45 |
Hyogo |
|
Electrical Characteristics of MAGFET With On-Chip Coil Hirokazu Hashimoto (The Univ. of Tokyo), Makoto Ikeda, Kunihiro Asada (VDEC) ICD2007-59 |
MAGFET ( Magnetic MOS Field-Effect Transistor ) is one of the magnetic sensors, which is capable of sensing a magnetic f... [more] |
ICD2007-59 pp.129-134 |
ICD, VLD |
2007-03-08 17:10 |
Okinawa |
Mielparque Okinawa |
[Invited Talk]
Measurements and reduction of power line noises in SoCs Makoto Ikeda, Kunihiro Asada (Tokyo Univ.) |
This paper describes power bounce measurement technique in SoCs and active substrate noise reduction techniques. Noise m... [more] |
VLD2006-139 ICD2006-230 pp.121-126 |
ICD, CPM |
2007-01-18 09:25 |
Tokyo |
Kika-Shinko-Kaikan Bldg. |
Study on Active Substrate Noise Cancelling Technique using Power Line di/dt Detector Taisuke Kazama (Univ. of Tokyo), Makoto Ikeda, Kunihiro Asada (VDEC) |
[more] |
CPM2006-130 ICD2006-172 pp.7-12 |