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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD | 2024-01-29 16:35 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
High-speed division circuits using BCD codes Fumiya Kanai, Yuki Tanaka (Gunma Univ.)  VLD2023-89 RECONF2023-92 |
In recent years, the need for decimal arithmetic has increased. However, these have the disadvantage of being more expen... [more] | VLD2023-89 RECONF2023-92 pp.53-58 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 09:55 |
Online | Online | Study on Reverse Converters for RNS moduli set {2^k,2^n+1,2^n-1} using Signed-Digit numbers Takahiro Morii, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2021-50 CPSY2021-19 RECONF2021-58 |
In this study, we propose reverse converters for moduli set ${2^k,2^n+1,2^n-1}$ that convert residue number system to we... [more] | VLD2021-50 CPSY2021-19 RECONF2021-58 pp.7-12 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 16:20 |
Online | Online | Residual signed-digit number - residual binary number conversion algorithm Yuki Saba, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2020-51 CPSY2020-34 RECONF2020-70 |
By applying SD(Signed-Digit) number representation, redundant residue number representation including negative number ca... [more] | VLD2020-51 CPSY2020-34 RECONF2020-70 pp.69-74 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 17:35 |
Online | Online | High speed architectures of decimal counters Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2020-54 CPSY2020-37 RECONF2020-73 |
In this study, we propose new architectures for high speed decimal counters. The two kinds of counters are designed usin... [more] | VLD2020-54 CPSY2020-37 RECONF2020-73 pp.85-89 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-30 10:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Proposal of reduction method of calculations by using Leading Zero in the Extended Euclidean Algorithm Masaki Ogino, Yuki Tanaka, Shugang Wei (Gunma Univ.) VLD2018-73 CPSY2018-83 RECONF2018-47 |
The modular multiplication inverse is used to generate the secret key of the public key cryptosystem from the difficulty... [more] | VLD2018-73 CPSY2018-83 RECONF2018-47 pp.7-12 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 13:25 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set Kouhei Yamazaki, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2017-69 CPSY2017-113 RECONF2017-57 |
[more] | VLD2017-69 CPSY2017-113 RECONF2017-57 pp.43-48 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 17:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. | A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption Kazumasa Ishikawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2016-92 CPSY2016-128 RECONF2016-73 |
In this paper, we presented a new residue addition algorithm using Signed-Digit (SD) numbers for the applications such a... [more] | VLD2016-92 CPSY2016-128 RECONF2016-73 pp.147-152 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 10:30 |
Kanagawa | Hiyoshi Campus, Keio University | Error detection using residue signed-digit number arithmetic for arithmetic circuits Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ) VLD2014-136 CPSY2014-145 RECONF2014-69 |
For error detection of multiply-accumulate operation, a residue error detector can be considered for the VLSI implementa... [more] | VLD2014-136 CPSY2014-145 RECONF2014-69 pp.151-156 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 14:35 |
Kanagawa | Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic Junichi Asaoka, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2012-115 CPSY2012-64 RECONF2012-69 |
RSA encryption processing spends a lot of time on modular exponentiation of long word length, therefore the speed of the... [more] | VLD2012-115 CPSY2012-64 RECONF2012-69 pp.45-50 |
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| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 10:50 |
Kanagawa | Hiyoshi Campus, Keio University | A residue - weighted number conversion algorithm based on signed-digit arithmetic for a three-moduli set Masaya Arai, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2011-110 CPSY2011-73 RECONF2011-69 |
In this paper, a residue-weighted number conversion algorithm using SD(signed-digit) arithmetic for a moduli set \{$2^n$... [more] | VLD2011-110 CPSY2011-73 RECONF2011-69 pp.111-116 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-17 15:45 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Residue Arithmetic and FIR Filter Design Based on Minimal Signed-Digit Number Representation Rui Chen, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2010-96 CPSY2010-51 RECONF2010-65 |
Residue arithmetic based on a radix-two signed-digit (SD) number system was proposed.Compared to the design of conventio... [more] | VLD2010-96 CPSY2010-51 RECONF2010-65 pp.75-80 |
| COMP | 2006-09-26 10:30 |
Ishikawa | JAIST | Bipancyclicity and edge-bipancyclicity of Cayley graphs generated by transpositions Yuuki Tanaka (Gunma Univ.), Yosuke Kikuchi (Tsuyama National College of Tech.), Toru Araki (Iwate Univ.), Yukio Shibata (Gunma Univ.) |
Cycle is the most fundamental graph class. For a given graph, it is interest to find cycles of various length as subgr... [more] |
COMP2006-25 pp.1-8 |
| COMP | 2004-09-17 15:00 |
Hokkaido | Hokkaido University | A group action graph representation of the Kautz digraph Yuuki Tanaka, Yukio Shibata (Gunma Univ.) |
De Bruijn digraphs and shuffle-exchange graphs are known to be useful models for interconnection networks. They can be ... [more] |
COMP2004-32 pp.49-56 |
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