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Committee Date Time Place Paper Title / Authors Abstract Paper #
R 2008-06-20
14:55		 Tokyo Kikai-Shinko-Kaikan Bldg. Improvement of Quality Awareness through LSI Evaluation and Analysis -- Trial at University --
Masaru Sanada (KUT) R2008-19		 At the university, I have executed the trial to improve of quality awareness to the student. My laboratory has treated a... [more] R2008-19
pp.25-30
EMD, R 2008-02-15
10:40		 Kyoto   Development of Simple ESD Checker and it's Application -- Detection of ESD Checker and it's Application --
Norio Yamasaki, Masaru Sanada (KUT) R2007-59 EMD2007-114		 Simple Electro Static Discharge(ESD) tester has been developed for evaluating ESD sensitivity of LSI and studying ESD pr... [more] R2007-59 EMD2007-114
pp.1-6
R 2007-09-14
10:55		 Kochi Kochi Univ. of Technology Fault logic trace by Using Transistor Operating Point Analysis -- Diagnosis of Feed Back Fault with Oscillating Phenomenon --
Masaru Sanada, Tonoya Nakamura, Keishi Hashida (KUT) R2007-30		  [more] R2007-30
pp.5-10
ED, SDM, R 2006-11-24
13:00		 Osaka Central Electric Club [Invited Talk] Fault diagnosis technology based on transistor behavor analysis
Masaru Sanada (KUT) 		 [more] R2006-31 ED2006-176 SDM2006-194
pp.1-6
ICD, CPM 2005-01-28
11:45		 Tokyo Kikai-Shinko-Kaikan Bldg. On Observability Quantification for Fault Diagnosis of VLSI Circuits
Naoya Toyota, Seiji Kajihara, Xiaoqing Wen (KIT), Masaru Sanada (NEC Electoronics) 		In most fault diagnosis, logic values can be observed at primary outputs and scan flip-flops as observation points. Howe... [more] CPM2004-167 ICD2004-212
pp.31-34
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