| IEICE Technical Committee Submission System Conference Schedule |
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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SR | 2024-05-21 15:10 |
Kagoshima | Yokacenter (Kagoshima) (Primary: On-site, Secondary: Online) |
Input Resolution Prediction for Accelerating Deep Learning based Radio Frequency Fingerprinting Kazutoshi Hirose, Seiya Shibata, Taichi Ohtsuji, Takashi Takenaka (NEC) |
[more] | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:25 |
Hiroshima | Satellite Campus Hiroshima | Transparent Acceleration Method for Network Function Virtualization Using FPGA Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Baba Hiroshi (NEC)  RECONF2018-38 |
Network Function Virtualization (NFV) is becoming a new networking architecture for telecom carriers. While NFV reali... [more] |
RECONF2018-38 pp.21-26 |
| VLD | 2017-03-02 13:30 |
Okinawa | Okinawa Seinen Kaikan | [Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC) VLD2016-115 |
CPU-FPGA tightly coupled architecture is an emerging architecture where FPGA is tightly coupled with CPU. We introduce a... [more] | VLD2016-115 p.79 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 11:20 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Malisious tamper detector design with capacitance measurement for IoT devices in operation Ryosuke Kitayama (Waseda Univ.), Takashi Takenaka (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-66 DC2016-60 |
(To be available after the conference date) [more] | VLD2016-66 DC2016-60 pp.129-134 |
| RECONF | 2016-09-06 09:10 |
Toyama | Univ. of Toyama | [Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC) RECONF2016-32 |
CPU-FPGA tightly coupled architecture is an emerging architecture where FPGA is tightly coupled with CPU. We introduce a... [more] | RECONF2016-32 p.37 |
| VLD, CAS, MSS, SIP | 2016-06-16 13:20 |
Aomori | Hirosaki Shiritsu Kanko-kan | [Panel Discussion]
The Role of System and Signal Processing Subsociety
-- Encouragement and Development of Young Researchers -- Yoshinobu Kajikawa (Kansai Univ.), Shunsuke Koshita (Tohoku Univ.), Takashi Takenaka (NEC), Yuichi Tanaka (TUAT), Satoshi Yamane (Kanazawa Univ.) CAS2016-9 VLD2016-15 SIP2016-43 MSS2016-9 |
The four technical committees of System and Signal Processing Subsociety have been holding joint workshop since 2010. We... [more] | CAS2016-9 VLD2016-15 SIP2016-43 MSS2016-9 p.47 |
| DC, CPSY | 2015-04-17 13:25 |
Tokyo | A study of processor architecture suited for intelligent sensing system Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST) CPSY2015-8 DC2015-8 |
Sensor nodes are now important elements for the system of social infrastructure, and thus intelligent processing capabil... [more] | CPSY2015-8 DC2015-8 pp.43-48 |
|
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 17:20 |
Kanagawa | Hiyoshi Campus, Keio University | Double Caching Memcached Accelerator Eric Shun Fukuda, Tsunaki Sadahisa (Hokkaido Univ.), Hiroaki Inoue, Takashi Takenaka (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) VLD2013-117 CPSY2013-88 RECONF2013-71 |
[more] | VLD2013-117 CPSY2013-88 RECONF2013-71 pp.91-96 |
| ICD, IPSJ-ARC | 2013-01-31 15:25 |
Tokyo | [Invited Talk]
Real-Time Event Processing on Reconfigurable Hardware Hiroaki Inoue, Takashi Takenaka (NEC) ICD2012-124 |
[more] | ICD2012-124 p.25 |
|
| VLD | 2012-03-06 14:00 |
Oita | B-con Plaza | A loop pipeling method for irregular nested loops Takashi Takenaka, Kazutoshi Wakabayashi (NEC), Yuka Nakagoshi (NIS) VLD2011-126 |
This paper presents a behavioral synthesis method for pipelining irregular nested loops. An irregular nested loop is ... [more] |
VLD2011-126 pp.37-42 |
| CAS, NLP | 2011-10-20 15:20 |
Shizuoka | Shizuoka Univ. | [Invited Talk]
Accelerating C-Based Complex Event Processing on FPGAs Hiroaki Inoue, Takashi Takenaka (NEC) CAS2011-43 NLP2011-70 |
[more] | CAS2011-43 NLP2011-70 pp.61-66 |
| IN, NS (Joint) |
2011-03-03 10:30 |
Okinawa | Okinawa Convention Center | Decision Tree Based Flow Search Hardware Engine Combined with Linear Search Eita Kobayashi, Norio Yamagaki, Takashi Takenaka, Satoshi Kamiya, Masato Motomura (NEC) NS2010-203 |
Recently, multi-field packet classification is increasingly becoming more important to enable fine-grained flow control ... [more] | NS2010-203 pp.229-234 |
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