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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-04 14:30 |
Oita |
B-Con Plaza (Beppu) |
A Feasibility Study on Implementing Micro-ITRON Task Scheduler by Wired-logic Kouichi Araki (Godai Kaihatsu), Tomoaki Ukezono (Fukuoka Univ.) CPSY2015-20 |
Software overheads which are caused by task scheduler inside operating systems have possibility of fluctuation. It impai... [more] |
CPSY2015-20 pp.53-58 |
RECONF |
2013-09-19 11:25 |
Ishikawa |
Japan Advanced Institute of Science and Technology |
A Low Power Oriented Design Framework for Considering Reconfiguration Time on Embedded Systems Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2013-31 |
[more] |
RECONF2013-31 pp.67-72 |
RECONF |
2013-09-19 14:50 |
Ishikawa |
Japan Advanced Institute of Science and Technology |
Considerations of Constantize for Entries in Associative Memories Using Dynamic Partial Reconfiguration Tomoaki Ukezono, Koichi Araki (JAIST) RECONF2013-36 |
In general, memories which can be referenced by associative search will enlarge hardware size and extend delay for refer... [more] |
RECONF2013-36 pp.97-102 |
RECONF |
2011-09-27 09:25 |
Aichi |
Nagoya Univ. |
A Design Framework for relieving a HW Bottleneck FPGAs Connected with a High-Speed Data Bus Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2011-33 |
As reconfigurable devices with a PCI-Express interface appear in the market, the data transfer speed between the reconfi... [more] |
RECONF2011-33 pp.63-68 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 10:45 |
Fukuoka |
Kyushu University |
An Effective Processing Method for Parallel Loops on FPGA with PCI-Express Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2010-47 |
As FPGAs with a PCI-Express Interface appear in the market, the data transter speed between FPGA and other units, such a... [more] |
RECONF2010-47 pp.49-54 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 14:15 |
Fukuoka |
Kitakyushu Science and Research Park |
A Method of Processing Data-Parallel Tasks on Multi-Context Reconfigurable Processor Koichi Araki, Yukinori Sato, Yasushi Inoguchi (Japan Advanced Institute of Science and Technology) RECONF2008-41 |
A Multi-context Reconfigurable Processor (MRP) can treat various tasks with hardware. However, in the case of treating a... [more] |
RECONF2008-41 pp.15-20 |
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