| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 13:15 |
Online | Online | A Study on Technology mapping method for Scalable Logic Module Izumi Kiuchi, Yuya Nakazato (Kumamoto Univ.), Qian Zhao (KIT), Masahiro Iida (Kumamoto Univ.)  VLD2021-68 CPSY2021-37 RECONF2021-76 |
The LUT (Lookup Table) , which is widely used as the logic cell in FPGA (Field Programmable Gate Array）, can implement a... [more] | VLD2021-68 CPSY2021-37 RECONF2021-76 pp.108-113 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 12:45 |
Online | Online | SLM based FPGA-IP soft core Yuya Nakazato, Hiroaki Koga (Kumamoto Univ.), Zhao Qian (KIT), Motoki Amagasaki, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) VLD2020-61 CPSY2020-44 RECONF2020-80 |
In the recent edge computing infrastructure, MEC (Multi-access Edge Computing) devices is considered to reduce the load ... [more] | VLD2020-61 CPSY2020-44 RECONF2020-80 pp.125-130 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 10:05 |
Ehime | Ehime Prefecture Gender Equality Center | DNN accelerator for AI edge computing Yasuhiro Nakahara, Juntaro Chikama, Motoki Amagasaki (Kumamoto Univ.), Zhao Qian (Kyutech), Masahiro Iida (Kumamoto Univ.) RECONF2019-38 |
Convolutional Neural Network (CNN), a kind of artificial intelligence for image recognition, is used in various fields ... [more] |
RECONF2019-38 pp.15-20 |
| RECONF | 2019-09-19 14:00 |
Fukuoka | KITAKYUSHU Convention Center | A CNN-based Net Wire Length Prediction Method for FPGA Placement Cost Function Yuki Katsuda, Ryota Watanabe, Qian Zhao, Takaichi Yoshida (Kyutech) RECONF2019-21 |
The placement of an FPGA design is performed using the simulated annealing algorithm with a cost function predicting wir... [more] | RECONF2019-21 pp.3-8 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:00 |
Hiroshima | Satellite Campus Hiroshima | Resources Utilization of Fine-grained Overlay Architecture Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) RECONF2018-37 |
This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures inc... [more] | RECONF2018-37 pp.15-20 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 10:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | hCODE 2.0: An Open-source Platform for FPGA Cluster System Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2017-27 DC2017-33 |
In recent years, major cloud providers such as Amazon and Microsoft are improving cloud applications using FPGAs. By in... [more] |
VLD2017-27 DC2017-33 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking Keishiro Akashi, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2017-42 |
In recent years,Three-dimensional (3D) field-programmable gate arrays(FPGAs) are expected to offer higher logic density ... [more] | RECONF2017-42 pp.31-36 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:55 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Development of power estimation tool for three dimensional FPGA Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-46 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2016-46 pp.35-40 |
| RECONF | 2016-09-06 10:55 |
Toyama | Univ. of Toyama | A Study of Methodology and Tools for Open-source FPGA Accelerators Takuya Nakamichi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-34 |
Today's information and communication society requires more and higher-performance computing devices with the constraint... [more] | RECONF2016-34 pp.45-50 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-19 11:05 |
Kanagawa | Hiyoshi Campus, Keio University | FPGA routing structure based on H-Tree topology Yuki ishii, Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2015-78 CPSY2015-110 RECONF2015-60 |
FPGA(Fiele Programmable Gate Array) has many routing resources in order to provide the flexibility. These routing resour... [more] | VLD2015-78 CPSY2015-110 RECONF2015-60 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 11:15 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Study of HW/SW Co-design Framework based on the Virtualization Technology Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2015-52 |
One challenge for the heterogeneous computing with the FPGA is to bridge the development gap between SW and HW design. T... [more] | RECONF2015-52 pp.21-26 |
| RECONF | 2015-06-19 12:00 |
Kyoto | Kyoto University | An Area Optimization of 3D FPGA with high speed inter-layer communication link Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-4 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2015-4 pp.17-22 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 11:05 |
Kanagawa | Hiyoshi Campus, Keio University | Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-120 CPSY2014-129 RECONF2014-53 |
The 3D IC technology is being researched to build better performance LSIs in a variety of applications when the process ... [more] | VLD2014-120 CPSY2014-129 RECONF2014-53 pp.41-46 |
| RECONF | 2014-09-18 14:10 |
Hiroshima | Prototype of fault tolerant FPGA using 65nm CMOS process Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-18 |
我々はSoC（System on a Chip）に搭載されるFPGA-IP（Field Programmable Gate Array Intellectual Property）コアに焦点をあてたFT-FPGA（Fault Tolera... [more] |
RECONF2014-18 pp.7-12 |
|
| RECONF | 2013-05-21 11:25 |
Kochi | Kochi Prefectural Culture Hall | A defect-robust FPGA-IP core architecture Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-13 |
In this paper, we propose fault-tolerant FPGA -IP cores for system LSI. Unlike discrete FPGAs, in which the integration... [more] |
RECONF2013-13 pp.67-72 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 10:00 |
Kanagawa | A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2012-109 CPSY2012-58 RECONF2012-63 |
3D LSIs promise More than Moore integration by packing a great deal of functionality on a chip, while improving performa... [more] | VLD2012-109 CPSY2012-58 RECONF2012-63 pp.13-18 |
|
| RECONF | 2012-09-19 13:15 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | A Design Framework for Reconfigurable IPs with VLSI CADs Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-41 |
The conventional FPGA design CAD flows evaluate FPGA architecture by implementing benchmarks through the following steps... [more] | RECONF2012-41 pp.101-106 |
| RECONF | 2010-09-17 09:50 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-32 |
As the size of integrated circuit has reached the nanoscale, embedded memories are more sensitive to single event upset ... [more] | RECONF2010-32 pp.85-90 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-26 14:55 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Design of Reconfigurable Logic Device based on Variable Grain Logic Cell Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2009-79 CPSY2009-61 RECONF2009-64 |
We propose a variable grain logic cell（VGLC）architecture. Its key feature is variable granularity which helps to create ... [more] | VLD2009-79 CPSY2009-61 RECONF2009-64 pp.59-64 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 15:10 |
Kanagawa | A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-121 CPSY2008-83 RECONF2008-85 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | VLD2008-121 CPSY2008-83 RECONF2008-85 pp.177-182 |
|
[Return to Top Page]