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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
EMCJ, MICT
(Joint)
2024-03-15
10:55
Shimane   Analysis of BPSD onset time to improve BPSD prediction performance with environmental and vital sensor data
Tatsunoshin Shinmi (The Univ. of Electro-Communications), Naoya Tokiwa (RAKUS Partners), Junichi Shibata, Toshikazu Suzuki (iD), Takehiko Kashiwagi (The Univ. of Electro-Communications), Tatsuya Moe (RAKUS Partners), Kaito Kamura, Hyuta Onuma, Shunichi Tano, Yasuhiro Minami (The Univ. of Electro-Communications) MICT2023-79
Behavioral and psychological symptoms of dementia (BPSD) that develop in patients with dementia not only impose a heavy ... [more] MICT2023-79
pp.12-16
LOIS 2023-03-13
12:45
Okinawa
(Primary: On-site, Secondary: Online)
Estimation of Behavioral and Psychological Symptoms of Dementia (BPSD) using Environmental and Vital Sensor Data
Yasuhiro Minami (UEC), Naoya Tokiwa (RAKUS Partners), Junichi Shibata, Toshikazu Suzuki (iD), Takehiko Kashiwagi, Tano Shunichi (UEC) LOIS2022-48
 [more] LOIS2022-48
pp.23-28
ICD, SDM 2012-08-02
09:35
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido A 40-nm 256-Kb Sub-10 pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme
Shusuke Yoshimoto, Masaharu Terada, Yohei Umeki, Shunsuke Okumura (Kobe Univ.), Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2012-64 ICD2012-32
 [more] SDM2012-64 ICD2012-32
pp.7-12
ICD 2012-04-24
13:00
Iwate Seion-so, Tsunagi Hot Spring (Iwate) [Invited Talk] 57% Faster Read, 31% Lower Read Energy, 256-Times Faster Injection 6T-SRAM with a Carrier-Injection Scheme to Pinpoint and Repair Disturb Fails
Kousuke Miyaji (Univ. of Tokyo), Toshikazu Suzuki (Panasonic), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) ICD2012-12
 [more] ICD2012-12
pp.61-66
ICD 2012-04-24
13:50
Iwate Seion-so, Tsunagi Hot Spring (Iwate) 0.4V SRAM with Bit Line Swing Suppression Charge Share Hierarchical Bit Line Scheme
Shinichi Moriwaki, Atsushi Kawasumi (STARC), Toshikazu Suzuki (Panasonic), Yasue Yamamoto, Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) ICD2012-13
 [more] ICD2012-13
pp.67-71
ICD 2012-04-24
14:15
Iwate Seion-so, Tsunagi Hot Spring (Iwate) A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura (Kobe Univ.), Toshikazu Suzuki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-14
This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-... [more] ICD2012-14
pp.73-78
ICD 2011-04-19
11:20
Hyogo Kobe University Takigawa Memorial Hall 0.5-V, 5.5-nsec Access Time, Bulk-CMOS 8T SRAM with Suspended Bit-Line Read Scheme
Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara (STARC) ICD2011-12
A low-voltage high-speed bulk-CMOS 8T SRAM is proposed. A novel 8-transistor (8T) memory cell with a complementary read ... [more] ICD2011-12
pp.65-70
ICD, SDM 2006-08-18
12:30
Hokkaido Hokkaido University A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses
Toshikazu Suzuki (Matsushita), Hiroyuki Yamauchi (Fukuoka Institute of Technology Univ.), Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu (Matsushita)
A guarantee obligation of keeping the cell-margin against a simultaneously read and write (R/W) disturbed accesses in th... [more] SDM2006-149 ICD2006-103
pp.137-141
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