IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SCE 2021-08-06
15:00
Online Online High-Throughput Low-Latency Single-Flux-Quantum Circuits with Feedback Path
Ryota Kashima, Ikki Nagaoka, Tomoki Nakano, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki (Nagoya Univ.) SCE2021-5
We have introduced bit-parallel processing into high-speed, low-power microprocessors based on single-flux-quantum circu... [more] SCE2021-5
pp.19-24
SCE 2021-01-19
15:25
Online Online Investigation of Operating Frequency of Low-Power Single-Flux-Quantum Circuits
Manami Kuniyoshi, Ken Murase, Ikki Nagaoka, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki (Nagoya Univ.) SCE2020-22
To reduce the power consumption of single-flux-quantum circuits, it is an effective method to reduce the critical curren... [more] SCE2020-22
pp.30-35
SCE 2020-01-17
13:15
Kanagawa   [Poster Presentation] High-Throughput Gate-Level-Pipelined SFQ Multipliers
Ikki Nagaoka, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita (Nagoya Univ.), Koji Inoue (Kyushu Univ.), Akira Fujimaki (Nagoya Univ.) SCE2019-30
 [more] SCE2019-30
pp.1-4
SCE 2020-01-17
13:15
Kanagawa   [Poster Presentation] Design of Datapath for 8-bit Parallel SFQ Microprocessors with Gate-Level Pipelines
Ryota Kashima, Ikki Nagaoka, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Akira Fujimaki (Nagoya Univ.) SCE2019-31
 [more] SCE2019-31
pp.5-9
SCE 2020-01-17
13:15
Kanagawa   [Poster Presentation] Investigation of Timing Design by Using Low-Power SFQ Shift Registers
Manami Kuniyoshi, Ken Murase, Ikki Nagaoka, Kyosuke Sano, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki (Nagoya Univ) SCE2019-48
 [more] SCE2019-48
pp.75-78
SCE 2019-01-23
13:30
Tokyo   Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors
Ikki Nagaoka (Nagoya Univ), Yuki Hatanaka (Mitsubishi Elec), Yuichi Matsui (Nagoya Univ), Koki Ishida (Kyushu Univ), Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita (Nagoya Univ), Takatsugu Ono, Koji Inoue (Kyushu Univ), Akira Fujimaki (Nagoya Univ) SCE2018-30
We have started development of high-throughput single-flux-quantum (SFQ) microprocessors with the aim of higher throughp... [more] SCE2018-30
pp.29-34
 Results 1 - 6 of 6  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan