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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-24
14:20
Kanagawa Raiosha, Hiyoshi Campus, Keio University An Approach to Approximate Multiplier Optimization
Xinpei Zhang, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. Tokyo) VLD2019-88 CPSY2019-86 RECONF2019-78
 [more] VLD2019-88 CPSY2019-86 RECONF2019-78
pp.205-210
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-24
14:45
Kanagawa Raiosha, Hiyoshi Campus, Keio University Partial synthesis method based on Column-wise verification for integer multipliers
Jian Gu, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2019-89 CPSY2019-87 RECONF2019-79
Partial logic synthesis is a method that most parts of the target circuits are fixed and the missing portions can be log... [more] VLD2019-89 CPSY2019-87 RECONF2019-79
pp.211-216
VLD, IPSJ-SLDM 2019-05-15
15:25
Tokyo Ookayama Campus, Tokyo Institute of Technology SRAM-Based Synthesis for Multi-Output Gates
Xingming Le, Amir Masoud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo) VLD2019-4
Conventionally a circuit is represented as a network of single-output gates. In this paper, we propose an implementation... [more] VLD2019-4
pp.25-30
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-30
11:20
Kanagawa Raiosha, Hiyoshi Campus, Keio University An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-74 CPSY2018-84 RECONF2018-48
This paper proposes an incremental ATPG method to deal with multiple stuck-at faults. In order to generate the test set ... [more] VLD2018-74 CPSY2018-84 RECONF2018-48
pp.13-18
VLD, IPSJ-SLDM 2018-05-16
13:30
Fukuoka Kitakyushu International Conference Center Partial logic synthesis by using sum of products or product of sums based quantified boolean formulae
Xiaoran Han, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-1
documentclass[a4paper,11pt]{jarticle}
usepackage{kws}
usepackage{amssymb}
usepackage{amsmath,array,graphicx}
... [more]
VLD2018-1
pp.1-5
VLD, IPSJ-SLDM 2017-05-10
13:30
Fukuoka Kitakyushu International Conference Center VLD2017-1 In this paper, we present techniques to automatically generate high-level C description after ECO (Engineering Change Or... [more] VLD2017-1
pp.1-6
VLD, CAS, MSS, SIP 2016-06-16
10:10
Aomori Hirosaki Shiritsu Kanko-kan Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient
Conrad JinYong Moore, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. of Tokyo) CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3
As fabricated circuitry gets larger and denser, modern industrial ATPG techniques which focus on the detection of single... [more] CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3
pp.13-18
 Results 1 - 7 of 7  /   
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