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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2023-09-15 13:50 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Abstraction of Processor-FPGA Communication in Reconfigurable Virtual Accelerator (ReVA) Eriko Maeda, Kazuki Yaguchi, Shunya Kawai, Daichi Teruya (TUAT), Yasunori Osana (Kumamoto Univ.), Takehumi Miyoshi (Wasalabo), Hironori Nakajo (TUAT)  RECONF2023-30 |
In recent years, hardware acceleration for HPC and AI has become a challenge due to the lack of resources and the comple... [more] | RECONF2023-30 pp.46-51 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80 |
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] | VLD2022-57 RECONF2022-80 pp.7-12 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 15:35 |
Online | Online | Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA) Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT) VLD2021-72 CPSY2021-41 RECONF2021-80 |
In recent years, the amount of computation and data in HPC, AI, and other computational processing has become increasing... [more] | VLD2021-72 CPSY2021-41 RECONF2021-80 pp.132-137 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 13:10 |
Online | Online | Automated architecture exploration on Scala-based hardware development environment Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) VLD2020-62 CPSY2020-45 RECONF2020-81 |
In recent years, reconfigurable architectures such as FPGAs have been attracting more and more attention. Design Space... [more] |
VLD2020-62 CPSY2020-45 RECONF2020-81 pp.131-136 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:35 |
Ehime | Ehime Prefecture Gender Equality Center | Domain Knowledge-aware Machine Learning System with Rule-based Guiding Tomoaki Shikina, Daichi Teruya, Hironori Nakajo (TAT) CPSY2019-44 |
Data-driven methods in machine learning rely only on the statistical nature of the data. Therefore, its predictions coul... [more] | CPSY2019-44 pp.23-28 |
| RECONF | 2019-05-09 15:20 |
Tokyo | Tokyo Tech Front | High Level Synthesis of Recursive Description in a CPU+FPGA Co-design framework based on Ruby Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) RECONF2019-6 |
(To be available after the conference date) [more] | RECONF2019-6 pp.29-34 |
| RECONF | 2018-05-24 15:20 |
Tokyo | GATE CITY OHSAKI | A design of autoscale mechanism using high level synthesis tool for autonomous distributed system Daichi Teruya, Hironori Nakajo (TUAT) RECONF2018-9 |
Since cloud computing has become widespread for various purposes, it is drawing attention to use FPGAs. When utilizing ... [more] |
RECONF2018-9 pp.45-50 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 09:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Overview of an HLS Framework Surpporting IoT/CPS Development Daichi Teruya, Hironori Nakajo (TUAT) VLD2017-77 CPSY2017-121 RECONF2017-65 |
We expect reduce CPU resource consumptions by offloading processing stream data, which are incessantly generated such a... [more] |
VLD2017-77 CPSY2017-121 RECONF2017-65 pp.89-94 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 09:00 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Overview of an HLS Framework Surpporting IoT/CPS Development Daichi Teruya, Hironori Nakajo (TUAT) VLD2016-80 CPSY2016-116 RECONF2016-61 |
[more] | VLD2016-80 CPSY2016-116 RECONF2016-61 pp.61-66 |
| RECONF | 2016-05-20 10:45 |
Kanagawa | FUJITSU LAB. | A Sound Field Visualizer with Java-based High Level Synthesis Tool and CoRAM Architecture Synthesis Framework Daichi Teruya, Daichi Miyazaki, Hironori Nakajo (TUAT) RECONF2016-20 |
Currently the number of devices which uses multiple sensors has been increasing due to recent significant interest on th... [more] | RECONF2016-20 pp.97-102 |
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