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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 37 of 37 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICSS 2015-03-04
15:55
Okinawa Meio Univiersity Evaluation on Malware Classification by Combining Traffic Analysis and Fuzzy Hashing of Malware Binary
Shohei Hiruta, Yukiko Yamaguchi, Hajime Shimada, Hiroki Takakura (Nagoya Univ.) ICSS2014-96
Recent cyber attacks frequently use variants of malware programs where existing functions are drastically improved and n... [more] ICSS2014-96
pp.199-204
IA 2014-11-06
15:30
Overseas Thailand Network Access Control by FPGA-Based Network Switch using HW/SW Cooperated IDS
Shun Yanase, Hajime Shimada, Yukiko Yamaguchi, Hiroki Takakura (Nagoya Univ.) IA2014-52
In recent years, cyber targeted attacks are becoming so sophisticated so that countermeasures for them is becoming impor... [more] IA2014-52
pp.91-96
CPSY 2014-10-10
14:15
Chiba Meeting Room 303, International Conference Hall, Makuhari-Messe Study of Processor Core for Many-core Architecture Combining ALU Cascading and 3-way In-order Execution
Hajime Shimada (Nagoya Univ.), Ryotaro Kobayashi (Toyohashi Univ. of Tech.) CPSY2014-53
Recent many-core processor frequently utilizes 2-way in-order execution core which is diverted from
high-performance em... [more]
CPSY2014-53
pp.37-42
ICSS, ISEC, SITE, EMM, IPSJ-CSEC, IPSJ-SPT [detail] 2014-07-03
11:05
Hokkaido San-Refure Hakodate Implementation of FPGA Section for Anomaly Detection Acceleration by HW/SW Cooperation
Shun Yanase, Hajime Shimada, Yukiko Yamaguchi, Hiroki Takakura (Nagoya Univ.) ISEC2014-16 SITE2014-11 ICSS2014-20 EMM2014-16
Anomaly-based Intrusion Detection System (anomaly IDS) is an approach of the IDS which creates a discrimination circuit ... [more] ISEC2014-16 SITE2014-11 ICSS2014-20 EMM2014-16
pp.75-80
ICSS, IA 2014-06-06
13:50
Hyogo Takikawa Memorial Hall, Kobe University Implementation of the Administration Policy Description Method on Automatic Network Organization System
Minori Shiota, Yukiko Yamaguchi, Hajime Shimada, Hiroki Takakura (Nagoya Univ.) IA2014-10 ICSS2014-10
To confront recent sophisticated targeted attacks, we have to consider a information system to prevent the destruction ... [more] IA2014-10 ICSS2014-10
pp.49-54
ICSS, IPSJ-SPT 2014-03-28
13:55
Okinawa Meio Univiersity Proposal of malware classification method based on pattern similarity of traffic
Hyoyoung Lim, Yukiko Yamaguchi, Hajime Shimada, Hiroki Takakura (Nagoya Univ.) ICSS2013-83
 [more] ICSS2013-83
pp.149-154
CPSY 2013-11-08
09:00
Hiroshima   Low Energy Consumption Oriented Heterogeneous Clustered Processor by Renewing A Part of Register Value
Shoma Kawai, Ryotaro Kobayashi (Toyohashi Univ. of Tech.), Hajime Shimada (Nagoya Univ.) CPSY2013-39
Recently, as technology advances, microprocessor performance has increased. But, improving processor performance is caus... [more] CPSY2013-39
pp.1-6
CPSY 2013-11-08
09:20
Hiroshima   Evaluation of a Dependable Interrupt Interface by Bundled Interrupt Request Lines
Hayato Nomura (Toyohashi Univ. of Tech.), Hajime Shimada (Nagoya Univ.), Ryotaro Kobayashi (Toyohashi Univ. of Tech.) CPSY2013-40
Conventional processors are exposed to not only on-chip transient faults caused by radiation and permanent failures due ... [more] CPSY2013-40
pp.7-12
IA 2013-10-10
14:00
Overseas Konkuk Univ., Seoul Proposal of a Network Control System to Detect, Analyze and Mitigate Targeted Cyber Attacks
Hirokazu Hasegawa, Yukiko Yamaguchi, Hajime Shimada, Hiroki Takakura (Nagoya Univ.) IA2013-26
Recently, targeted cyber attacks have been so sophisticated that we cannot detect them at early stage of intrusion.
The... [more]
IA2013-26
pp.1-6
VLD 2013-03-06
15:35
Okinawa Okinawa Seinen Kaikan Robust Redundant Circuit Structure to Mitigate Wearout by Reversing Register Values
Shogo Okada, Masaki Masuda (Kyoto Inst. of Tech.), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2012-162
 [more] VLD2012-162
pp.147-152
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-28
13:25
Miyazaki NewWelCity Miyazaki Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops
Shogo Okada, Masaki Masuda (KIT), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (KIT) VLD2011-59 DC2011-35
Soft-error rates are becoming larger due to process scaling. Various ways of prediction for soft-error
are being tried.... [more]
VLD2011-59 DC2011-35
pp.43-48
RECONF 2009-05-14
17:00
Fukui   [Invited Talk] Development of Interactive Supercomputing Environment
Shin-ichiro Mori (Univ. of Fukui), Tomohiro Kuroda, Naoto Kume (Kyoto Univ.), Yoshihiro Kuroda (Osaka Univ.), Megumi Nakao, Hajime Shimada, Yasuhiko Nakashima (NAIST), Shinji Tomita (Kyoto Univ.) RECONF2009-8
Toward the Era of Interactive Supercomputing,, the authors have promoted the five years research project on the Real-Tim... [more] RECONF2009-8
pp.43-48
ICD, IPSJ-ARC 2008-05-13
09:00
Tokyo   Branch Target Predictor Utilizing Context Base Value Predictor
Tetsurou Hirashima (NRI), Hajime Shimada (Kyoto Univ.), Shinobu Miwa (TUAT), Shinji Tomita (Kyoto Univ.)
A control dependency is one of the factor which limits instruction level parallelism. To alleviate limitation from the c... [more] ICD2008-17
pp.1-6
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-17
10:40
Kanagawa Hiyoshi Campus, Keio University Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation
Takahiro Kawahara, Shinobu Miwa, Hajime Shimada (Kyoto Univ.), Shin-ichiro Mori (Univ. of Fukui), Shinji Tomita (Kyoto Univ.) VLD2007-122 CPSY2007-65 RECONF2007-68
We are developing the parallel volume rendering accelerator VisA.VisA communicates with one-way link over DVI-D which is... [more] VLD2007-122 CPSY2007-65 RECONF2007-68
pp.25-30
ICD, IPSJ-ARC 2007-06-01
14:15
Kanagawa   The Dynamic Instruction Scheduler for ALU Cascading
Kosuke Ogata, Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita (Kyoto Univ.)
 [more] ICD2007-32
pp.91-96
ICD, IPSJ-ARC 2006-06-08
11:30
Kanagawa   Dynamic Control Mechanisms for Pipeline Stage Unification Based on Program Phase Detection
Jun Yao, Hajime Shimada (Kyoto Univ.), Yasuhiko Nakashima (NAIST), Shin-ichiro Mori (Fukui Univ.), Shinji Tomita (Kyoto Univ.)
To reduce the power consumption in mobile processors, a method called Pipeline Stage Unification (PSU) is previously des... [more] ICD2006-43
pp.19-24
RECONF, CPSY, VLD, IPSJ-SLDM 2006-01-18
14:30
Kanagawa   A Parallel Volume Rendering System implemented with High-Speed DVI Link
Dai Okamura, Yusuke Noda, Shinobu Miwa, Hajime Shimada (Kyoto Univ), Yasuhiko Nakashima (Kyoto Univ/JST), Shin-ichiro Mori, Shinji Tomita (Kyoto Univ)
(Advance abstract in Japanese is available) [more] VLD2005-104 CPSY2005-60 RECONF2005-93
pp.43-46
 Results 21 - 37 of 37 [Previous]  /   
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