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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 40 of 68 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
13:25
Fukuoka Centennial Hall Kyushu University School of Medicine Explicit and Unconditionally Stable Finite Difference Scheme for the Fast Transient Analysis of the Power Distribution Network
Norio Nishizaki, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) VLD2012-97 DC2012-63
 [more] VLD2012-97 DC2012-63
pp.219-224
VLD, CAS, MSS, SIP 2012-07-03
09:30
Kyoto Kyoto Research Park Fast Simulation of Multiconductor Transmission Lines Using Nodal Block Relaxation (NBR) Method
Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2012-15 VLD2012-25 SIP2012-47 MSS2012-15
This paper describes a nodal block relaxation (NBR) method in which the block relaxation method is applied to the nodal ... [more] CAS2012-15 VLD2012-25 SIP2012-47 MSS2012-15
pp.81-85
EMCJ 2012-06-01
10:50
Tokyo TMU Akihabara Satellite Campus Circuit/Electromagnetic Hybrid Simulation of Electrostatic Discharge Events
Tsuyoshi Takada, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) EMCJ2012-20
In this paper, we describe a hybrid simulation technique for electrostatic discharge (ESD) events in contact discharge m... [more] EMCJ2012-20
pp.65-70
EMCJ 2012-06-01
11:15
Tokyo TMU Akihabara Satellite Campus Time-Domain Electromagnetic Simulation Based on Leapfrog Scheme and Retarded Partial Element Equivalent Circuit (PEEC) Method
Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) EMCJ2012-21
This paper describes a full-wave transient simulation technique based on the retarded partial element equivalent circuit... [more] EMCJ2012-21
pp.71-76
AP 2012-03-15
15:45
Shizuoka Chuo public hall (Atami City) [Special Talk] Packaging Oriented CAE Technology for Chip/Package/Board Co-design
Hideki Asai (Shizuoka Univ.)
 [more]
CAS, NLP 2011-10-20
13:05
Shizuoka Shizuoka Univ. Fast Electromagnetic Field Simulation by GPGPU-based Massively Parallel ADE-FDTD Method
Yuta Inoue, Masaki Unno, Shuichi Aono, Hideki Asai (Shizuoka Univ.) CAS2011-38 NLP2011-65
With the progress of high-density integration technology and increasing operation frequency, a variety of power and sign... [more] CAS2011-38 NLP2011-65
pp.31-36
CAS, NLP 2011-10-20
13:30
Shizuoka Shizuoka Univ. Fast Circuit Simulation Based on Improved Latency Insertion Method with Predictor-Corrector Method
Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2011-39 NLP2011-66
This report describes an improved latency insertion method (LIM) with predictor-corrector method for the fast transient ... [more] CAS2011-39 NLP2011-66
pp.37-42
CAS, NLP 2011-10-20
14:20
Shizuoka Shizuoka Univ. Fast Simulation of Multiconductor System with Nonlinear Devices by Using Block-Latency Insertion Method and Reduced Order Model
Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2011-41 NLP2011-68
This paper describes a fast circuit simulation technique based on the block-latency insertion method (block-LIM) and a m... [more] CAS2011-41 NLP2011-68
pp.49-54
EMCJ, IEE-EMC 2011-06-24
13:35
Kyoto Kyoto Univ. Effective Electromagnetic Simulation Techniques of Angled Interconnection Pattern by Using Hybrid Implicit-Explicit (HIE)-FDTD and Conformal FDTD (CFDTD) Methods
Hideaki Muraoka, Masaki Unno, Shuichi Aono, Hideki Asai (Shizuoka Univ.) EMCJ2011-39
Due to orthogonal grids in conventional finite-difference time-domain (FDTD) methods, difficulty in modeling a complicat... [more] EMCJ2011-39
pp.31-36
EMCJ, IEE-EMC 2011-06-24
14:00
Kyoto Kyoto Univ. Fast Simulation Technique Based on Block-Latency Insertion Method for Large Linear Circuit with CMOS Inverters
Yusuke Hizawa, Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) EMCJ2011-40
For an analysis of large networks including nonlinear active devices and coupled elements, conventional SPICE-like simul... [more] EMCJ2011-40
pp.37-42
EMCJ, ITE-BCT 2011-03-11
13:50
Tokyo Kikai-Shinko-Kaikan Bldg. Hybrid FDTD Method Based on Explicit/ADI Schemes and Its Application to 2-D Analysis
Kyosuke Kuroda, Hideki Asai (Shizuoka Univ.) EMCJ2010-123
In this report, we propose a hybrid finite-difference time-domain (FDTD) method, where the FDTD method and the ADI-FDTD ... [more] EMCJ2010-123
pp.27-32
EMCJ, ITE-BCT 2011-03-11
14:30
Tokyo Kikai-Shinko-Kaikan Bldg. Multirate Block-LIM for Fast Transient Analysis of Tightly Coupled Transmission Lines
Yuta Inoue, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) EMCJ2010-124
The block-Latency Insertion Method (block-LIM) is one of the techniques for fast transient analyses of large scale linea... [more] EMCJ2010-124
pp.33-38
EMCJ, ITE-BCT 2011-03-11
14:55
Tokyo Kikai-Shinko-Kaikan Bldg. Equivalent Circuit Modeling and Optimization for Reduction of Common-Mode Current in Automotive EMC
Shingo Okada (Shizuoka Univ.), Takanori Uno (DENSO CORP.), Hideki Asai (Shizuoka Univ.) EMCJ2010-125
In this paper, first, we introduce a practical equivalent circuit modeling for the automotive electromagnetic compatibil... [more] EMCJ2010-125
pp.39-44
EMCJ, IEE-EMC 2010-12-10
13:45
Aichi Chukyo Univ. Toyoda Campus Electromagnetic Field Simulation Based on Bi-Directional SI-FDTD Method and its Estimation
Shuichi Aono, Masaki Unno, Hideki Asai (Shizuoka Univ.) EMCJ2010-91
 [more] EMCJ2010-91
pp.57-62
MSS, CAS 2010-11-19
10:25
Osaka Kansai Univ. ADE-LIM for the Fast Transient Simulation of Multiconductor Transmission Lines and Its Estimation
Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2010-78 CST2010-51
This report describes an application techique of the alternating direction explicit-latency insertion mehod (ADE-LIM) to... [more] CAS2010-78 CST2010-51
pp.71-76
MSS, CAS 2010-11-19
10:50
Osaka Kansai Univ. High-speed Electromagnetic Simulation Based on 3-D HIE-FDTD Method by Using GPU
Masaki Unno, Hideki Asai (Shizuoka Univ.) CAS2010-79 CST2010-52
 [more] CAS2010-79 CST2010-52
pp.77-82
MW, EMCJ 2010-10-21
15:30
Akita Akita Univ. 3D HIE-FDTD Method for the Network Including Lumped Elements and Its Estimation
Masaki Unno, Hideki Asai (Shizuoka Univ.) EMCJ2010-57 MW2010-92
 [more] EMCJ2010-57 MW2010-92
pp.31-36
CAS
(2nd)
2010-10-06
11:45
Chiba Makuhari Messe [Invited Talk] PI/SI/EMI simulation technology for high-speed electronic design
Hideki Asai (Shizuoka Univ.)
A variety of noise problems, such as signal integrity, power integrity and electromagnetic interference have become very... [more]
CAS, MSS, VLD, SIP 2010-06-21
09:25
Hokkaido Kitami Institute of Technology High-speed Transient Simulation of Power Distribution Network Based on ADE-LIM
Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2010-2 VLD2010-12 SIP2010-23 CST2010-2
An analysis of power distribution network is emphasized to supply stable power to a printed circuit board and packages i... [more] CAS2010-2 VLD2010-12 SIP2010-23 CST2010-2
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-02
13:15
Kochi Kochi City Culture-Plaza [Invited Talk] PI/SI/EMI for Chip/Package/Board Co-Design
Hideki Asai (Shizuoka Univ.) CPM2009-138 ICD2009-67
 [more] CPM2009-138 ICD2009-67
pp.23-27
 Results 21 - 40 of 68 [Previous]  /  [Next]  
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