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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2009-02-16 16:10 |
Tokyo | A Secure Scan Design Approach using Extended de Bruijn Graph Hideo Fujiwara, Marie Engelene J. Obien (NAIST)  DC2008-78 |
Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. T... [more] | DC2008-78 pp.61-66 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 11:20 |
Fukuoka | Kitakyushu Science and Research Park | A Reconfigurable Wrapper Design for Testing Cores with Multi-Clock Domains Takashi Yoshida, Tomokazu Yoneda, Hideo Fujiwara (Nara Institute of Science and Technology) VLD2008-82 DC2008-50 |
This paper presents an optimization method for designing reconfigurable test wrappers for cores with multiple clock doma... [more] | VLD2008-82 DC2008-50 pp.133-138 |
| VLD, CAS, SIP | 2008-06-27 09:40 |
Hokkaido | Hokkaido Univ. | An Approach to RTL-GL Path Mapping Based on Functional Equivalence Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara (NAIST) CAS2008-21 VLD2008-34 SIP2008-55 |
Information on false paths in a circuit is useful for design and test. The use of this information may contribute not o... [more] | CAS2008-21 VLD2008-34 SIP2008-55 pp.13-18 |
| VLD, CAS, SIP | 2008-06-27 10:00 |
Hokkaido | Hokkaido Univ. | On the Test Environment Generation Problem Using Assignment Decision Diagrams Yuki Shimizu (NAIST), Chia Yee Ooi (UTM), Hideo Fujiwara (NAIST) CAS2008-22 VLD2008-35 SIP2008-56 |
In this paper, we consider a problem of test environment generation for functional register-transfer level (RTL) circuit... [more] | CAS2008-22 VLD2008-35 SIP2008-56 pp.19-24 |
| DC | 2008-02-08 11:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Secure Scan Design Based on Ballanced Structure Muneo Hasegawa, Michiko Inoue, Hideo Fujiwara (NAIST) DC2007-73 |
In this paper, we propose a secure scan design which protects scan-based side channel attacks to the circuits containing... [more] | DC2007-73 pp.39-44 |
| DC | 2008-02-08 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | RTL False Path Identification Using High Level Synthesis Information Naotsugu Ikeda, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2007-77 |
This paper proposes a method of RTL false path identification using high level synthesis information. By using the false... [more] | DC2007-77 pp.63-68 |
| DC | 2008-02-08 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Methods for State Observable FSMs to Increase Defect Coverage Under Test Length Constraint Ryoichi Inoue, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) DC2007-78 |
We proposed a fault-independent test generation method for logical fault testing of state-observable FSMs and a fault-de... [more] | DC2007-78 pp.69-76 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 14:40 |
Fukuoka | Kitakyushu International Conference Center | Thermal-Aware Test Scheduling with Cycle-Accurate Power Profiles and Test Partitioning Thomas Edison Yu, Tomokazu Yoneda (NAIST), Krishnendu Chakrabarty (Duke Univ.), Hideo Fujiwara (NAIST) VLD2007-84 DC2007-39 |
Higher power densities and the non-linear spatial distribution of heat of VLSI chips put greater emphasis on chip-packag... [more] | VLD2007-84 DC2007-39 pp.13-18 |
| CAS, SIP, VLD | 2007-06-22 11:30 |
Hokkaido | Hokkaido Tokai Univ. （Sapporo) | Power Constrained IP Core Wrapper Design with Partitioned Clock Domains Thomas Edison Yu, Tomokazu Yoneda (NAIST), Danella Zhao (Unive. of Louisiana), Hideo Fujiwara (NAIST) CAS2007-25 VLD2007-41 SIP2007-55 |
Rapid developments in VLSI technology has made it possible to embed whole system components onto a single chip, called S... [more] | CAS2007-25 VLD2007-41 SIP2007-55 pp.37-42 |
| CAS | 2007-01-30 12:20 |
Ehime | Ehime Univ. | A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake (NAIST), Mineo Kaneko (JAIST), Hideo Fujiwara (NAIST) |
[more] | CAS2006-76 pp.37-42 |
| RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2006-11-28 16:10 |
Fukuoka | Kitakyushu International Conference Center | Test Scheduling for SoCs with Built-In Self-Repairable Memory Cores Yusuke Fukuda, Tomokazu Yoneda, Hideo Fujiwara (NAIST) |
This paper presents a power-constrained test scheduling mehtod for SoCs with built-in self repairable memories which are... [more] | VLD2006-61 DC2006-48 pp.59-64 |
| ICD, IPSJ-ARC | 2006-06-08 15:30 |
Kanagawa | Design for Testability of Software-Based Self-Test for Processors Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) |
In this paper, we propose a design for testability method for test programs of software-based self-test using test progr... [more] | ICD2006-48 pp.49-54 |
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| VLD, IPSJ-SLDM | 2006-05-12 11:15 |
Ehime | Ehime University | Power-Conscious Microprocessor-Based Testing of System-on-Chip Fawnizu Azmadi Hussin, Tomokazu Yoneda (NAIST), Alex Orailoglu (Univ. of California), Hideo Fujiwara (NAIST) |
In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and resp... [more] | VLD2006-10 pp.25-30 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-01 09:30 |
Fukuoka | Kitakyushu International Conference Center | Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure Kosuke Yabuki, Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a method of path delay fault testing for application-specific interconnects in field-programmable ga... [more] | VLD2005-61 ICD2005-156 DC2005-38 pp.1-6 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-01 10:20 |
Fukuoka | Kitakyushu International Conference Center | Reconfigurable Wrapper Design for Multi Clock Domain Cores Under Power Constraints Yu Tanaka, Tomokazu Yoneda, Hideo Fujiwara (NAIST) |
This paper presents a re-configurable wrapper design for scan-designed multi-clock domain cores in system-on-chips. The ... [more] | VLD2005-63 ICD2005-158 DC2005-40 pp.13-18 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-02 09:55 |
Fukuoka | Kitakyushu International Conference Center | A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a broadside test generation method for transition faults in partial scan circuits. In order to gene... [more] |
VLD2005-77 ICD2005-172 DC2005-54 pp.7-12 |
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