Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF, VLD |
2024-01-30 13:20 |
Kanagawa |
AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2023-94 RECONF2023-97 |
This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path... [more] |
VLD2023-94 RECONF2023-97 pp.81-86 |
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] |
2022-01-24 10:20 |
Online |
Online |
Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2021-51 CPSY2021-20 RECONF2021-59 |
This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level s... [more] |
VLD2021-51 CPSY2021-20 RECONF2021-59 pp.13-18 |
HWS, VLD [detail] |
2021-03-03 14:55 |
Online |
Online |
Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware
implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
HWS, VLD [detail] |
2020-03-05 10:30 |
Okinawa |
Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Motor Current Signature Analysis Based On-Line Fault Detection of DC Motor Naoki Osako (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-111 HWS2019-84 |
This article presents a method for online detection of DC motors' fault based on current signature analysis.
While cu... [more] |
VLD2019-111 HWS2019-84 pp.101-106 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2020-01-23 11:25 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Full Hardware Synthesis of FreeRTOS-Based Systems Wakako Nakano, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2019-70 CPSY2019-68 RECONF2019-60 |
[more] |
VLD2019-70 CPSY2019-68 RECONF2019-60 pp.105-110 |
HWS, VLD |
2019-03-01 10:00 |
Okinawa |
Okinawa Ken Seinen Kaikan |
Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85 |
This paper presents a method of automatically synthesizing a hardware
design from a set of source codes for a real-time... [more] |
VLD2018-122 HWS2018-85 pp.175-180 |
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] |
2018-01-18 17:00 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Distributed Memory Architecture for High-Level Synthesis from Erlang Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2017-75 CPSY2017-119 RECONF2017-63 |
This paper presents a distributed memory architecture for dedicated
hardware automatically synthesized from Erlang prog... [more] |
VLD2017-75 CPSY2017-119 RECONF2017-63 pp.77-82 |
VLD |
2016-02-29 15:00 |
Okinawa |
Okinawa Seinen Kaikan |
High-Level Synthesis of Embedded Systems Controller from Erlang Hinata Takabeyashi, Nagisa Ishiura, Kagumi Azuma (Kwansei Gakuin Univ), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2015-114 |
This article presents a method of specifying the behavior of embedded systems' control by a subset of Erlang and synthes... [more] |
VLD2015-114 pp.19-24 |
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] |
2016-01-21 13:50 |
Kanagawa |
Hiyoshi Campus, Keio University |
Binary Synthesis Implementing External Interrupt Handler as Independent Module Naoya Ito, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2015-106 CPSY2015-138 RECONF2015-88 |
[more] |
VLD2015-106 CPSY2015-138 RECONF2015-88 pp.215-220 |
DC, CPSY |
2015-04-17 13:25 |
Tokyo |
|
A study of processor architecture suited for intelligent sensing system Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST) CPSY2015-8 DC2015-8 |
Sensor nodes are now important elements for the system of social infrastructure, and thus intelligent processing capabil... [more] |
CPSY2015-8 DC2015-8 pp.43-48 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-29 16:45 |
Kanagawa |
Hiyoshi Campus, Keio University |
Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-133 CPSY2013-104 RECONF2013-87 |
This article presents a method of synthesizing hardware that accelerates specified sections of binary programs. The acce... [more] |
VLD2013-133 CPSY2013-104 RECONF2013-87 pp.185-190 |
CPSY, VLD, RECONF, IPSJ-SLDM [detail] |
2013-01-16 16:25 |
Kanagawa |
|
Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu Shunsuke Satake (Kwansei Gakuin Univ), Nagisa Ishiura, Shimpei Tamura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ), Hiroyuki Kanbara (ASTEM) VLD2012-119 CPSY2012-68 RECONF2012-73 |
This article presents an improvement over the hardware accelerator
tightly coupled with a CPU. While the previously pr... [more] |
VLD2012-119 CPSY2012-68 RECONF2012-73 pp.69-73 |
VLD, CPSY, RECONF, IPSJ-SLDM [detail] |
2012-01-26 09:00 |
Kanagawa |
Hiyoshi Campus, Keio University |
Merge of Functions in High-Level Synthesis using Assembly Codes as Intermediate Representation Fumiaki Takashima, Nagisa Ishiura, Makoto Orino (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2011-106 CPSY2011-69 RECONF2011-65 |
This article presents a method of merging functions during high-level synthesis whose inputs are assembly codes generate... [more] |
VLD2011-106 CPSY2011-69 RECONF2011-65 pp.89-94 |
VLD, CPSY, RECONF, IPSJ-SLDM [detail] |
2012-01-26 09:25 |
Kanagawa |
Hiyoshi Campus, Keio University |
High-Level Synthesis of Hardware Relinkable to Software Makoto Orino, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Fumiaki Takashima (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2011-107 CPSY2011-70 RECONF2011-66 |
This article presents a method of synthesizing {\em relinkable} hardware for hardware/software codesign utilizing high-l... [more] |
VLD2011-107 CPSY2011-70 RECONF2011-66 pp.95-100 |
VLD, CPSY, RECONF, IPSJ-SLDM |
2009-01-29 16:10 |
Kanagawa |
|
Extension of High Level Synthesis system CCAP for AMP multi-core system desin Yoshiyuki Ishimori, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Nagoya Univ.), Hiroyuki Kanbara (ASTEM) VLD2008-105 CPSY2008-67 RECONF2008-69 |
[more] |
VLD2008-105 CPSY2008-67 RECONF2008-69 pp.81-86 |
VLD, ICD, DC, IPSJ-SLDM |
2005-12-02 11:00 |
Fukuoka |
Kitakyushu International Conference Center |
Handling of Variables and Functions for Software Compatible Hardware Synthesizer CCAP Kenichi Nishiguchi, Nagisa Ishiura, Masanari Nishimura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Nagoya Univ.), Yutetsu Takatsukasa, Manabu Kotani (Kyoto Univ.) |
We are developing a high-level synthesis tool named CCAP (C Compatible Architecture Prototyper), which synthesizes arbit... [more] |
VLD2005-79 ICD2005-174 DC2005-56 pp.19-24 |