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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 35 of 35 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-30
10:05
Miyazaki NewWelCity Miyazaki Capture power reduction in multi-cycle test structure
Hisato Yamaguchi, Makoto Matsuzono, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) VLD2011-83 DC2011-59
Power consumption during Built-In Self-Test(BIST) is far larger than that of normal operation. Therefore, it may lead to... [more] VLD2011-83 DC2011-59
pp.179-183
DC 2011-06-24
16:20
Tokyo Kikai-Shinko-Kaikan Bldg. Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification
Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto (KIT), Yuta Yamato (NAIST), Xiaoqing Wen, Seiji Kajihara (KIT), Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Verazel (Lirmm) DC2011-13
In this paper, we present a test vector modification method to reduce launch-to-capture power for LOS scheme. The propos... [more] DC2011-13
pp.29-34
DC 2011-02-14
10:25
Tokyo Kikai-Shinko-Kaikan Bldg. Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors
Ryota Sakai, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.), Masao Aso, Hiroshi Furukawa (RMS), Yuta Yamato (Fukuoka Ind. Sci & Tech/Fundation FIST), Seiji Kajihara (Kyushu Inst. of Tech.) DC2010-60
Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This h... [more] DC2010-60
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-29
16:05
Fukuoka Kyushu University Rotating Test and Pattern Partitioning for Field Test
Senling Wang, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Insti. Tech.)
 [more]
DC 2010-02-15
14:10
Tokyo Kikai-Shinko-Kaikan Bldg. On Calculation of Delay Test Quality for Test Cubes and X-filling
Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech./JTS) DC2009-73
This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns... [more] DC2009-73
pp.51-56
DC 2010-02-15
15:40
Tokyo Kikai-Shinko-Kaikan Bldg. High Speed X-Fault Diagnosis with Partial X-Resolution
Kohei Miyase (Kyushu Inst. of Tech.), Yusuke Nakamura (Panasonic Communications Software Co.,Ltd.), Yuta Yamato, Xiaoqing Wen, Seiji Kajihara (Kyushu Inst. of Tech.) DC2009-76
Defects behavior of ultra small size and high speed LSI is getting complicated. It makes localization of fault site and ... [more] DC2009-76
pp.69-74
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-03
14:05
Kochi Kochi City Culture-Plaza Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity
Isao Beppu (Kyushu Institute of Tech), Kohei Miyase (Kyushu Institute of Tech/JST), Yuta Yamato (Kyushu Institute of Tech), Xiaoqing Wen, Seiji Kajihara (Kyushu Institute of Tech/JST) VLD2009-55 DC2009-42
Increase of power dissipation and IR-drop during scan-shifting operation and/or capture operation is still challenging p... [more] VLD2009-55 DC2009-42
pp.95-100
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-04
14:25
Kochi Kochi City Culture-Plaza A Path Selection Method of Delay Test for Transistor Aging
Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST) VLD2009-65 DC2009-52
With the advanced VLSI process technology, it is important for reliability of VLSIs to deal with faults caused by aging.... [more] VLD2009-65 DC2009-52
pp.167-172
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
13:50
Fukuoka Kitakyushu Science and Research Park A Capture-Safe Test Generation Scheme for At-speed Scan Testing
Atsushi Takashima, Yuta Yamato, Hiroshi Furukawa, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyusyu Institute of Technology) VLD2008-62 DC2008-30
Capture-safety, defined as the avoidance of any timing error due to unduly high switching activity in capture mode durin... [more] VLD2008-62 DC2008-30
pp.13-18
DC 2008-06-20
16:15
Tokyo Kikai-Shinko-Kaikan Bldg Transistor Aging and Operational Environment of Logic Circuits
Masafumi Haraguchi (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.) DC2008-17
With the progress of integrated circuit technology, it is becoming important to consider circuit aging. In this work we ... [more] DC2008-17
pp.35-40
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
10:30
Fukuoka Kitakyushu International Conference Center A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing
Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT) VLD2007-71 DC2007-26
High power dissipation can occur when a response to the test vector is captured by flip-flops in at-speed scan testing, ... [more] VLD2007-71 DC2007-26
pp.7-12
R 2007-09-14
13:40
Kochi Kochi Univ. of Technology An expanded Per-Test X-Fault Diagnosis Method for LSI Circuits
Yusuke Nakamura, Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara (KIT), K. K. Saluja (Univ. of Wisconsin) R2007-33
The behavior of defects has become complex and more than one defects often occur in a single circuit due to shrinking fe... [more] R2007-33
pp.23-28
ICD, CPM 2007-01-19
13:00
Tokyo Kika-Shinko-Kaikan Bldg. A Constrained Test Generation Method for Low Power Testing
Yoshiaki Tounoue, Xiaoqing Wen, Seiji Kajihara (K I T), Kohei Miyase (JST), Tatsuya Suzuki, Yuta Yamato (K I T)
High Power dissipation when the response to a test vector is captured by flip-flops in scan testing which may cause exce... [more] CPM2006-148 ICD2006-190
pp.109-114
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2006-11-28
11:45
Fukuoka Kitakyushu International Conference Center Test relaxation for N-detection test patterns in broad-side delay testing
Kenjiro Taniguchi (Kyushu Inst. of Tech.), Kohei Miyase (JST), Seiji Kajihara, Xiaoqing Wen (Kyushu Inst. of Tech.)
 [more] VLD2006-57 DC2006-44
pp.35-40
VLD, ICD, DC, IPSJ-SLDM 2005-12-02
09:30
Fukuoka Kitakyushu International Conference Center On Low Capture Power Test Generation for Scan Testing
Tatsuya Suzuki, Xiaoqing Wen, Seiji Kajihara (K.I.T.), Kohei Miyase, Yoshihiro Minamoto (JST)
High switching activity occurs when the response to a test vector is captured by flip-flops during scan testing. This ma... [more] VLD2005-76 ICD2005-171 DC2005-53
pp.1-6
 Results 21 - 35 of 35 [Previous]  /   
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