IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 40 of 76 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2012-12-17
15:55
Tokyo Tokyo Tech Front [Poster Presentation] Instantaneous Heart Rate Detection Using Short-Time Autocorrelation for Wearable Healthcare Systems
Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-92
This report describes a robust method of Instantaneous Heart Rate (IHR) detection from noisy electrocardiogram (ECG) sig... [more] ICD2012-92
p.27
ICD 2012-12-17
15:55
Tokyo Tokyo Tech Front [Poster Presentation] Low-Power Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing
Tomoki Nakagawa, Shusuke Yoshimoto, Yuki Kitahara, Koji Yanagida, Yohei Umeki, Shunsuke Okumura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-98
In recent years, sensor network has attracted much attention in agricultural, medical, and disaster-prevention area to c... [more] ICD2012-98
p.41
ICD 2012-12-17
15:55
Tokyo Tokyo Tech Front [Poster Presentation] A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition
Yuki Miyamoto, Guangji He, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ) ICD2012-101
This paper describes a low-power VLSI chip for 60-kWord continuous speech recognition based on a context-dependent Hidde... [more] ICD2012-101
pp.49-53
ICD 2012-12-17
15:55
Tokyo Tokyo Tech Front [Poster Presentation] FPGA Implementation of HOG-based Real-Time Object Detection Processor
Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-105
Histogram of Oriented Gradients (HOG) is widely accepted feature descriptor for object detection. HOG is robust against ... [more] ICD2012-105
p.61
ICD, SDM 2012-08-02
09:10
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido A Variation-Aware Low-Voltage Set-Associative Cache with Mixed-Associativity
Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2012-63 ICD2012-31
In this paper, we propose the mixed associativity scheme using 7T/14T SRAM, which can reduce the minimum operating volta... [more] SDM2012-63 ICD2012-31
pp.1-6
ICD, SDM 2012-08-02
09:35
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido A 40-nm 256-Kb Sub-10 pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme
Shusuke Yoshimoto, Masaharu Terada, Yohei Umeki, Shunsuke Okumura (Kobe Univ.), Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2012-64 ICD2012-32
 [more] SDM2012-64 ICD2012-32
pp.7-12
ICD 2012-04-24
14:15
Iwate Seion-so, Tsunagi Hot Spring (Iwate) A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura (Kobe Univ.), Toshikazu Suzuki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2012-14
This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-... [more] ICD2012-14
pp.73-78
ICD 2012-04-24
15:15
Iwate Seion-so, Tsunagi Hot Spring (Iwate) Low-Energy Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy
Yohei Umeki, Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) ICD2012-16
This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful ... [more] ICD2012-16
pp.85-90
ICD 2012-04-24
16:05
Iwate Seion-so, Tsunagi Hot Spring (Iwate) A 128-bit Chip Identification Generating Scheme Exploiting SRAM Bitcells with Failure Rate of 4.45X 10-19
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ., JST CREST) ICD2012-18
We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitc... [more] ICD2012-18
pp.97-102
SS 2012-03-13
15:20
Okinawa Tenbusu-Naha Handsfree Voice Interface for Home Network Service Using a Microphone Array Network
Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Noriyuki Matsubara, Koji Kugata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SS2011-69
The voice control is a promising user interface for the home network system (HNS). In our previous interface, a user had... [more] SS2011-69
pp.73-78
ICD, IPSJ-ARC 2012-01-20
10:30
Tokyo   Associativity-Variable Cache to Adaptively Expand Operating Voltage Margin
Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (JST) ICD2011-139
This paper presents a dependable cache memory for which associativity can be reconfigured dynamically. The proposed asso... [more] ICD2011-139
pp.55-60
ICD, IPSJ-ARC 2012-01-20
16:20
Tokyo   A 75-Variable MIQP Solver Processor for Real-Time Robot Control
Masanori Nishino, Hiroki Noguchi, Yusuke Shimai, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2011-144
This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time... [more] ICD2011-144
pp.103-107
ICD 2011-12-16
13:50
Osaka   A 284-uW 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers
Keisuke Okuno, Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2011-132
We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS tr... [more] ICD2011-132
pp.149-154
ICD 2011-12-16
14:25
Osaka   0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation
Shusuke Yoshimoto, Kosuke Yamaguchi, Shunsuke Okumura, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.) ICD2011-133
We propose 7T/14T FD-SOI SRAM with a substrate bias control mechanism. The 14T configuration suppresses intra-die variat... [more] ICD2011-133
pp.155-160
ICD 2011-12-16
14:50
Osaka   Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
Yohei Umeki, Shusuke Yoshimoto, Takurou Amashita, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) ICD2011-134
This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline s... [more] ICD2011-134
pp.161-166
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-30
10:05
Miyazaki NewWelCity Miyazaki A 40nm 144mW VLSI Processor for Realtime 60k Word Continuous Speech Reconginion
Takanobu Sugahara, Guangji He, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) CPM2011-164 ICD2011-96
We have developed a low power VLSI chip for 60k-word real-time continuous speech recognition based on HMM(Hidden Markov ... [more] CPM2011-164 ICD2011-96
pp.79-84
CPSY 2011-10-21
09:30
Hyogo   Dependability evaluation of processor using the dependable SRAM by system-level fault injection
Yusuke Takeuchi, Yohei Nakata (Kobe Univ.), Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (Hitachi), Shunsuke Okumura, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) CPSY2011-25
We propose a fault-injection system (FIS) that can inject faults such as read/write margin failures and soft errors into... [more] CPSY2011-25
pp.1-6
CPSY 2011-10-21
15:50
Hyogo   A Feasibility Study of Home Services Using a Microphone Array Network
Shimpei Soda, Shinsuke Matsumoto, Masahide Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) CPSY2011-36
The home network system (HNS), which provides value-added services by orchestrating networked home appliances, equipment... [more] CPSY2011-36
pp.61-66
ICD 2011-04-19
09:30
Hyogo Kobe University Takigawa Memorial Hall 0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM
Koji Yanagida, Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Hiroshi Kawaguchi (Kobe Univ.) ICD2011-8
We proposes a dependable dual-port SRAM with 9T/18T bitcell structure. The proposed SRAM has two operating modes: a 9T n... [more] ICD2011-8
pp.43-48
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
09:50
Fukuoka Kyushu University Fault-Injection using Virtualized Environment for Validating Automotive Systems
Yasuhiro Ito (Hitachi.), Yohei Nakata, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Yasuo Sugure, Shigeru Oho (Hitachi.) VLD2010-73 DC2010-40
Fault Injection System: a system level co-simulation environment with fault-injection in memory access was developed. It... [more] VLD2010-73 DC2010-40
pp.119-123
 Results 21 - 40 of 76 [Previous]  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan