Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPSY, DC, IPSJ-ARC (Joint) [detail] |
2018-08-01 18:30 |
Kumamoto |
Kumamoto City International Center |
Takeharu Ikezoe, Hideharu Amano (Keio Univ.), Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) CPSY2018-32 |
[more] |
CPSY2018-32 pp.229-234 |
VLD, HWS (Joint) |
2018-03-02 10:30 |
Okinawa |
Okinawa Seinen Kaikan |
Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122 |
As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that ena... [more] |
VLD2017-122 pp.199-204 |
VLD |
2017-03-01 14:25 |
Okinawa |
Okinawa Seinen Kaikan |
A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-103 |
This paper describes a nonvolatile Flip-Flop (NVFF) circuit to implement Nonvolatile Power Gating. We proposed a new NVF... [more] |
VLD2016-103 pp.7-12 |
VLD, CAS, MSS, SIP |
2016-06-17 09:50 |
Aomori |
Hirosaki Shiritsu Kanko-kan |
Design and Evaluation of MTJ-based Standard Cell Memory Junya Akaike, Masaru Kudo, Kimiyoshi Usami (SIT) CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 |
With the spread of portable devices, products with high performance and long battery life are required. In this paper, w... [more] |
CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 pp.103-108 |
VLD |
2016-03-01 17:05 |
Okinawa |
Okinawa Seinen Kaikan |
Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control Yusuke Yoshida, Masaru Kudo, Kimiyoshi Usami (SIT) VLD2015-130 |
In recent years, energy harvesting and sensor node have attracted a lot of attention. Therefore, a memory which can redu... [more] |
VLD2015-130 pp.111-116 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:20 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2015-57 DC2015-53 |
This paper describes a sleep control technique using leakage monitor circuit to implement Fine-Grain Power Gating (FGPG)... [more] |
VLD2015-57 DC2015-53 pp.129-134 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:25 |
Kagoshima |
|
Development of a fine-grain power-gated CPU "Geyser-3" and adaptive power-off control to the temperature Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech.), Weihan Wang, Hideharu Amano (Keio Univ), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ of Agriculture and Tech), Masaaki Kondo (Univ of Elec-Comm), Hiroshi Nakamura (Univ of Tokyo) VLD2013-80 DC2013-46 |
[more] |
VLD2013-80 DC2013-46 pp.135-140 |
CPSY, VLD, RECONF, IPSJ-SLDM [detail] |
2013-01-16 15:00 |
Kanagawa |
|
Automatic generation of the Power-Switch Driver Circuit and evaluation in Power-gating design implementation Makoto Miyauchi, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2012-116 CPSY2012-65 RECONF2012-70 |
[more] |
VLD2012-116 CPSY2012-65 RECONF2012-70 pp.51-56 |
CPSY, VLD, RECONF, IPSJ-SLDM [detail] |
2013-01-16 16:00 |
Kanagawa |
|
Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72 |
Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit duri... [more] |
VLD2012-118 CPSY2012-67 RECONF2012-72 pp.63-68 |
CPSY, VLD, RECONF, IPSJ-SLDM [detail] |
2013-01-16 17:00 |
Kanagawa |
|
Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide (SOTB) Shinya Ajiro, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2012-120 CPSY2012-69 RECONF2012-74 |
Silicon on thin BOX(SOTB) is an FD-SOI device being possible to operate with ultra-low voltage of 0.4V and greatly chang... [more] |
VLD2012-120 CPSY2012-69 RECONF2012-74 pp.75-80 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 13:50 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
Control of Fine-Grain Power Gating by Detecting of the Virtual Ground Voltage Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2012-98 DC2012-64 |
This paper describes fine-grain control to power gate function units using the charge up phenomenon of the virtual groun... [more] |
VLD2012-98 DC2012-64 pp.225-230 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:30 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
Energy Measurement and Analysis of ProcessingElement for Ultra Low Voltage Sachio Anzai, Masaru Kudo, Yuya Ota, Kazuki Ota, Kimiyoshi Usami (Sibaura Inst. Tech.) VLD2012-99 DC2012-65 |
The ALU of the ProcessingElement at 65nm process was operated by the ultra-low voltage, and delay time and survey of pow... [more] |
VLD2012-99 DC2012-65 pp.231-236 |
VLD |
2012-03-07 15:15 |
Oita |
B-con Plaza |
Power-Switch Drive-circuit generation for Ground-Bounce reduction using the Genetic-Programming Makoto Miyauchi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-142 |
Ground Bounce noise is a serious problem Power Gating technology. In this research, as compared with the Daisy Chain whi... [more] |
VLD2011-142 pp.133-138 |
VLD |
2012-03-07 16:05 |
Oita |
B-con Plaza |
Leakage Energy Reduction of Sub-Threshold Circuits by Body Bias Control for Power Switch Ryo Mitsuhashi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-144 |
Power Gating (PG) is one of the technologies for reducing leakage energy. The effectiveness of leakage energy reduction ... [more] |
VLD2011-144 pp.145-150 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 11:20 |
Miyazaki |
NewWelCity Miyazaki |
Power-Gating Circuit Scheme for Transient-Glitch Energy Reduction Yuya Ohta, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-90 DC2011-66 |
In fine-grain power gating which performs cell-by-cell power gating (PG) , energy overhead consumed at sleep-in and slee... [more] |
VLD2011-90 DC2011-66 pp.221-226 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 14:50 |
Fukuoka |
Kyushu University |
Optimal adder architecture in ultra low voltage domain Nao Konishi, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. Tech.) VLD2010-81 DC2010-48 |
Circuit performance is evaluated for several adder architectures with wiring capacitance extracted from layout at 65nm p... [more] |
VLD2010-81 DC2010-48 pp.173-178 |