Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD |
2016-03-01 09:25 |
Okinawa |
Okinawa Seinen Kaikan |
A Screening Circuit for Intrusion Detection of High-Speed Networks and its FPGA Implementation Hiroki Takaguchi, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) VLD2015-119 |
[more] |
VLD2015-119 pp.49-54 |
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] |
2016-01-19 14:20 |
Kanagawa |
Hiyoshi Campus, Keio University |
GPGPU Implementation of the MSD Method for Outlier Detection and Its Experimental Evaluation Shotaro Asano, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2015-83 CPSY2015-115 RECONF2015-65 |
In recent years,as the information,communication and sensing technologies advance,data streams have been continuously gr... [more] |
VLD2015-83 CPSY2015-115 RECONF2015-65 pp.37-42 |
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] |
2016-01-20 15:05 |
Kanagawa |
Hiyoshi Campus, Keio University |
A Parallel Algorithm for Realizing the MacCormack Scheme in Computational Fluid Dynamics and its FPGA Implementation Yusuke Haga, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) VLD2015-93 CPSY2015-125 RECONF2015-75 |
In many partial differential equation models used in various applications such as fluid analysis, their analytical solut... [more] |
VLD2015-93 CPSY2015-125 RECONF2015-75 pp.137-142 |
VLD |
2015-03-04 11:35 |
Okinawa |
Okinawa Seinen Kaikan |
A parallel Algorithm for Realizing the Lax-Friedrichs Scheme in Computational Fluid Dynamics and its FPGA Implementation Yusuke Haga, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) VLD2014-180 |
In the model of partial differential equations used in complex numerical simulations such as fluid analysis, it is diffi... [more] |
VLD2014-180 pp.153-158 |
RECONF, CPSY, VLD, IPSJ-SLDM [detail] |
2015-01-30 09:10 |
Kanagawa |
Hiyoshi Campus, Keio University |
Intrusion Detection in High-Speed Networks with a Multi-Byte Transition NFA Shin'ichi Wakabayashi, Tomoaki Hashimoto, Ryohei Koishi, Hiroki Takaguchi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) VLD2014-133 CPSY2014-142 RECONF2014-66 |
[more] |
VLD2014-133 CPSY2014-142 RECONF2014-66 pp.133-138 |
RECONF, CPSY, VLD, IPSJ-SLDM [detail] |
2015-01-30 13:20 |
Kanagawa |
Hiyoshi Campus, Keio University |
Implementation of Sparse Matrix-Vector Multiplication on GPU and Its Application to the Conjugate Gradient Method Shotaro Asano, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2014-141 CPSY2014-150 RECONF2014-74 |
Numerical simulations are offten performed by converting complex partial differential equations into a system of discret... [more] |
VLD2014-141 CPSY2014-150 RECONF2014-74 pp.181-186 |
RECONF |
2014-09-18 16:35 |
Hiroshima |
|
A Time-division Multiplexing Method of Inter-FPGA Signals for Multi-FPGA Systems with Various Topologies Masato Inagi (Hiroshima City Univ.), Yuichi Nakamura (NEC), Yasuhiro Takashima (Univ. of Kitakyusyu), Shin'ichi Wakabayashi (Hiroshima City Univ.) RECONF2014-23 |
[more] |
RECONF2014-23 pp.35-40 |
VLD |
2014-03-04 10:05 |
Okinawa |
Okinawa Seinen Kaikan |
Parallel Tabu Search for the Motif Extraction Problem in Molecular Biology and its GPGPU Implementation Yuki Tanihara, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2013-144 |
[more] |
VLD2013-144 pp.61-66 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 08:55 |
Kanagawa |
Hiyoshi Campus, Keio University |
A Unified Software/Reconfigurable Hardware Approach to Solving the Maximum Clique Problem of Large Graphs Chikako Miura, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) VLD2013-103 CPSY2013-74 RECONF2013-57 |
We propose an algorithm to solve the maximum clique problem of large graphs. The proposed algorithm is a unified softwar... [more] |
VLD2013-103 CPSY2013-74 RECONF2013-57 pp.7-12 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:00 |
Kagoshima |
|
ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length Hiroki Nishiyama, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) RECONF2013-49 |
In this paper, we propose an ILP-based method for simultaneous optimal technology mapping, placement and routing for pro... [more] |
RECONF2013-49 pp.57-62 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 14:35 |
Kagoshima |
|
Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) RECONF2013-55 |
In this paper, we evaluate some logic and interconnection structures for MPLD, which is a basic architecture
for reconf... [more] |
RECONF2013-55 pp.87-92 |
VLD |
2013-03-05 14:55 |
Okinawa |
Okinawa Seinen Kaikan |
A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2012-150 |
Parallel routing methods using various parallel computing environments have been proposed in existing studies for reduci... [more] |
VLD2012-150 pp.83-88 |
CPSY, VLD, RECONF, IPSJ-SLDM [detail] |
2013-01-16 09:10 |
Kanagawa |
|
Architecture Evaluation of a Reconfigurable Device MPLD Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) VLD2012-107 CPSY2012-56 RECONF2012-61 |
In this paper, we discuss the detailed structure of MPLD, an architecture for
realizing reconfigurable devices. MPLD co... [more] |
VLD2012-107 CPSY2012-56 RECONF2012-61 pp.1-6 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:50 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
An ILP Formulation of Placement and Routing for PLDs Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ) VLD2012-75 DC2012-41 |
In this paper, we formulate the simultaneous technology mapping, placement and
routing problem for programmable gate a... [more] |
VLD2012-75 DC2012-41 pp.93-98 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 10:30 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
A Hardware Algorithm Using Dynamically Partially Reconfigurable FPGAs for Solving the Maximum Clique Problem of Large Graphs Chikako Miura, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) RECONF2012-53 |
In this paper, we propose a hardware algorithm to solve the maximum clique problem of large graphs, and show its impleme... [more] |
RECONF2012-53 pp.33-38 |
VLD |
2012-03-07 11:10 |
Oita |
B-con Plaza |
Implmentation of Look-ahead Assertion for Pattern-independent Regular Expression Matching Engine Yoichi Wakaba, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2011-136 |
In this paper, we propose a look-ahead assertion matching method for regular expression matching hardware engine. In net... [more] |
VLD2011-136 pp.97-102 |
VLD |
2012-03-07 13:45 |
Oita |
B-con Plaza |
A GPGPU Implementation of Approximate Regular Expression Matching Algorithm and Comparison with an FPGA Implementation Yuichiro Utan, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2011-139 |
Recently, to conduct more advanced approximate string matching, a systolic hardware algorithm for approximate string mat... [more] |
VLD2011-139 pp.115-120 |
VLD, CPSY, RECONF, IPSJ-SLDM [detail] |
2012-01-26 15:25 |
Kanagawa |
Hiyoshi Campus, Keio University |
Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ) |
(To be available after the conference date) [more] |
|
VLD |
2011-09-27 09:45 |
Fukushima |
University of Aizu |
Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City Univ.), Takashi Ishiguro (Taiyo Yuden) VLD2011-47 |
FPGAs realize a target circuit by realizing logic cells by LUTs and connecting wires among the logic cells by switch blo... [more] |
VLD2011-47 pp.37-42 |
RECONF |
2010-09-16 16:10 |
Shizuoka |
Shizuoka University (Faculty of Eng., Hall 2) |
An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN) RECONF2010-26 |
[more] |
RECONF2010-26 pp.49-54 |