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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 32 of 32 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2015-01-27
10:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] High Ion/Ioff Ge-source Ultrathin Body Strained-SOI Tunnel FETs -- Impact of Channel Strain, MOS Interfaces and Back Gate on the Electrical Properties --
Minsoo Kim, Yuki K. Wakabayashi, Ryosho Nakane, Masafumi Yokoyama, Mitsuru Takenaka, Shinichi Takagi (The Univ. of Tokyo) SDM2014-137
High performance operation of Ge-source/strained-Si-channel hetero-junction tunnel FETs is demonstrated. It is found tha... [more] SDM2014-137
pp.9-12
OPE, LQE 2014-12-19
14:50
Tokyo Kikai-Shinko-Kaikan, NTT Atsugi R&D center Thermal resistance improvement and low-resistance lateral PIN junction formation technique on III-V-OI wafers
Yuki Ikku, Mitsuru Takenaka, Shinichi Takagi (Univ. Tokyo) OPE2014-146 LQE2014-133
III-V CMOS photonics is a platform which enables strong optical confinement to the III-V waveguides by using III-V-on-In... [more] OPE2014-146 LQE2014-133
pp.37-40
OPE, LQE 2014-06-20
16:40
Tokyo   Small, low-crosstalk optical switches using III-V CMOS photonics platform
Yuki Ikku, Masafumi Yokoyama, Mitsuru Takenaka, Shinichi Takagi (Univ. of Tokyo) OPE2014-21 LQE2014-26
III-V CMOS photonics is a platform which enables strong optical confinement for the III-V waveguides by using III-V on i... [more] OPE2014-21 LQE2014-26
pp.39-42
SDM 2014-01-29
15:05
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] High Performance Sub-20-nm-Channel-Length Extremely-Thin Body InAs-on-Insulator Tri-Gate MOSFETs with High Short Channel Effect Immunity and Vth Tunability
S. H. Kim, Masafumi Yokoyama, Ryosho Nakane (Univ. of Tokyo), Osamu Ichikawa, Takenori Osada, Masahiko Hata (Sumitomo Chemical), Mitsuru Takenaka, Shinichi Takagi (Univ. of Tokyo) SDM2013-144
 [more] SDM2013-144
pp.39-42
SDM 2013-06-18
11:15
Tokyo Kikai-Shinko-Kaikan Bldg. Impact of metal gate electrodes on electrical properties of InGaAs MOS gate stacks
Chih-Yu Chang, Masafumi Yokoyama, Sang-Hyeon Kim (Univ. of Tokyo), Osamu Ichikawa, Takenori Osada, Masahiko Hata (Sumitomo Chemical), Mitsuru Takenaka, Shinichi Takagi (Univ. of Tokyo) SDM2013-50
Electrical properties of Al2O3 and HfO2/InGaAs metal-oxide-semiconductor (MOS) capacitors with Al, Au and Pd gate electr... [more] SDM2013-50
pp.33-37
SDM, ED
(Workshop)
2012-06-29
09:15
Okinawa Okinawa Seinen-kaikan [Invited Talk] III-V/Ge integration on Si platform for electronic-photonic integrated circuits
Mitsuru Takenaka, Shinichi Takagi (Univ. Tokyo)
We have investigated heterogeneous integration of III-Vs and Ge on the Si platform for electronics and photonics. Owing ... [more]
EMD, OPE, LQE, CPM 2010-08-26
15:00
Hokkaido Chitose Arcadia Plaza III-V CMOS platform technologies for high-performance electric-photonic integrated circuits
Mitsuru Takenaka, Masafumi Yokoyama, Masakazu Sugiyama, Yoshiaki Nakano, Shinichi Takagi (Univ. of Tokyo.) EMD2010-35 CPM2010-51 OPE2010-60 LQE2010-33
 [more] EMD2010-35 CPM2010-51 OPE2010-60 LQE2010-33
pp.45-48
ED, SDM 2010-07-01
10:45
Tokyo Tokyo Inst. of Tech. Ookayama Campus [Invited Talk] III-V/Ge CMOS technologies and heterogeneous integrations on Si platform
Shinichi Takagi, Mitsuru Takenaka (Univ. of Tokyo.) ED2010-78 SDM2010-79
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performanc... [more] ED2010-78 SDM2010-79
pp.119-124
SDM 2010-06-22
14:10
Tokyo An401・402 Inst. Indus. Sci., The Univ. of Tokyo Relationships among Interface Composition, Bonding Structures and MIS Properties at High-k/III-V Interfaces
Tetsuji Yasuda, Noriyuki Miyata, Yuji Urabe, Hiroyuki Ishii, Taro Itatani, Tatsuro Maeda (AIST), Hisashi Yamada, Noboru Fukuhara, Masahiko Hata (Sumitomo Chemical), Akihiro Ohtake (NIMS), Takuya Hoshii, Masafumi Yokoyama, Mitsuru Takenaka, Shinichi Takagi (Univ. of Tokyo) SDM2010-42
There has been a significant interest in the III-V channel MISFET technology which expectedly enables performance improv... [more] SDM2010-42
pp.49-54
SDM 2009-06-19
11:20
Tokyo An401・402 Inst. Indus. Sci., The Univ. of Tokyo Electrical Properties of Ge MIS Interface Defects
Noriyuki Taoka, Wataru Mizubayashi, Yukinori Morita, Shinji Migita, Hiroyuki Ota (MIRAI-NIRC), Shinichi Takagi (MIRAI-NIRC/Univ. of Tokyo) SDM2009-30
The response of majority and minority carriers with interface traps have been systematically investigated for Ge MIS int... [more] SDM2009-30
pp.21-26
SDM 2008-06-09
13:30
Tokyo An401・402, Inst. Indus. Sci., The Univ. of Tokyo [Tutorial Lecture] Current Status and Prospects of High Mobility Channel Technologies for High performance CMOS
Shinichi Takagi (Univ. of Tokyo/MIRAI-AIST) SDM2008-42
Saturation of CMOS performance has been evident in the present 45 nm technology and beyond because of the a variety of l... [more] SDM2008-42
pp.1-6
SDM 2007-06-08
15:05
Hiroshima Hiroshima Univ. ( Faculty Club) Characteristics of HfO2/Ge-nitride/Ge MIS structures
Tatsuro Maeda, Yukinori Morita, Masayasu Nishizawa (AIST), Shinichi Takagi (AIST/Univ. of Tokyo) SDM2007-50
 [more] SDM2007-50
pp.101-106
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