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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2018-04-20 10:20 |
Tokyo | [Invited Lecture]
An Implementation of 2RW Dual-Port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT Yohei Sawada, Yoshiki Yamamoto, Takumi Hasegawa, Hiroki Shinkawata, Makoto Yabuuchi (REL), Yoshihiro Shinozaki, Kyoji Ito (NSW), Shinji Tanaka, Nii Koji, Shiro Kamohara (REL)  ICD2018-8 |
[more] | ICD2018-8 pp.29-32 |
|
| SDM, ICD, ITE-IST [detail] | 2017-07-31 10:40 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | A 65 nm 1.0V 1.84ns Silicon-on-Thin-Box (SOTB) Embedded SRAM with 13.72 nW/Mbit Standby Power for Smart IoT Makoto Yabuuchi, Koji Nii, Shinji Tanaka (Renesas), Shinozaki Yoshihiro (Nippon Systemware), Yoshiki Yamamoto, Takumi Hasegawa, Hiroki Shinkawata, Shiro Kamohara (Renesas) SDM2017-33 ICD2017-21 |
[more] | SDM2017-33 ICD2017-21 pp.13-16 |
| SDM | 2016-10-26 15:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB CMOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitach), Koichiro Ishibashi (The Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (The Univ. of Tokyo) SDM2016-71 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2016-71 pp.15-20 |
| SDM | 2016-10-26 16:10 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias Yoshiki Yamamoto, Hideki Makiyama, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Shinkawata Hiroki, Shiro Kamohara, Yasuo Yamaguchi (Renesas), Nobuyuki Sugii (Hitachi), Tomoko Mizutani, Toshiro Hiramoro (UT) SDM2016-72 |
We demonstrated record 0.37V minimum operation voltage (VMIN) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks... [more] | SDM2016-72 pp.21-25 |
| SDM, ICD | 2015-08-25 10:55 |
Kumamoto | Kumamoto City | [Invited Talk]
Novel Single p+Poly-Si/Hf/SiON Gate Stack Technology on Silicon-on-Thin-Buried-Oxide (SOTB) for Ultra-Low Leakage Applications Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitachi), Tomoko Mizutani, Masaharu Kobayashi, Toshiro Hiramoto (UT) SDM2015-67 ICD2015-36 |
We demonstrate a cost effective 65-nm SOTB CMOS technology for ultra-low leakage applications. Novel single p+poly-Si/Hf... [more] | SDM2015-67 ICD2015-36 pp.53-57 |
| SDM | 2014-10-17 14:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Back-Bias Control technique for Suppression of Die-to-Die Delay Variability of SOTB MOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Yasuo Yamaguchi (LEAP), Koichiro Ishibashi (Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (Univ. of Tokyo) SDM2014-94 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2014-94 pp.61-68 |
| ICD, SDM | 2014-08-05 09:50 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | Statistical Analysis of Minimum Operation Voltage (Vmin) in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells Tomoko Mizutani (Univ. of Tokyo), Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii (LEAP), Toshiro Hiramoto (Univ. of Tokyo) SDM2014-72 ICD2014-41 |
The minimum operation voltage (Vmin) of fully depleted (FD) silicon-on-thin-BOX (SOTB) SRAM cells are measured and stati... [more] | SDM2014-72 ICD2014-41 pp.55-58 |
| ICD | 2014-04-18 09:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Yasuo Yamaguchi (LEAP), Tomoko Mizutani, Toshiro Hiramoto (UTokyo) ICD2014-11 |
We demonstrated record 0.37V minimum operation voltage (VMIN) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks... [more] | ICD2014-11 pp.53-57 |
| ICD, SDM | 2012-08-02 13:00 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | [Invited Lecture]
Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, The University of Tokyo) SDM2012-68 ICD2012-36 |
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation (ULV) CMOS with maximum power efficien... [more] | SDM2012-68 ICD2012-36 pp.29-32 |
| SDM, ED (Workshop) |
2012-06-29 09:45 |
Okinawa | Okinawa Seinen-kaikan | [Invited Talk]
Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, Univ. of Tokyo) |
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation CMOS with maximum power efficiency can... [more] | |
| SDM, ICD | 2011-08-26 09:00 |
Toyama | Toyama kenminkaikan | Evaluation of Variability in High-k/Metal-Gate MOSFET using Takeuchi Plot Tomoko Mizutani, Anil Kumar (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete) SDM2011-83 ICD2011-51 |
[more] | SDM2011-83 ICD2011-51 pp.65-68 |
| SDM, ICD | 2011-08-26 09:25 |
Toyama | Toyama kenminkaikan | Statistical Analysis of DIBL and Current-Onset Voltage (COV) Variability in Scaled MOSFETs Anil Kumar, Tomoko Mizutani (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete) SDM2011-84 ICD2011-52 |
[more] | SDM2011-84 ICD2011-52 pp.69-73 |
| ICD, SDM | 2010-08-27 13:20 |
Hokkaido | Sapporo Center for Gender Equality | Direct Measurement and Analysis of Static Noise Margin in SRAM Cells Using DMA TEG Toshiro Hiramoto, Makoto Suzuki, Takuya Saraya, Ken Shimizu (Univ. of Tokyo), Akio Nishida, Shiro Kamohara, Kiyoshi Takeuchi, Tohru Mogami (MIRAI-Selete) SDM2010-144 ICD2010-59 |
[more] | SDM2010-144 ICD2010-59 pp.111-114 |
| ICD, SDM | 2010-08-27 16:00 |
Hokkaido | Sapporo Center for Gender Equality | Random Drain Current Variation Caused by "Current-Onset Voltage" Variability in Scaled MOSFETs Tomoko Mizutani (Univ. of Tokyo), Takaaki Tsunomura (MIRAI-Selete), Anil Kumar (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete) SDM2010-150 ICD2010-65 |
It is revealed that drain current variability is fluctuated by “current-onset voltage” as well as threshold voltage VTH ... [more] | SDM2010-150 ICD2010-65 pp.143-148 |
| ICD, SDM | 2008-07-17 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Special Talk]
Present Status and Future Trend of Characteristic Variations in Scaled CMOS Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete), Kiyoshi Takeuchi, Takaaki Tsunomura (/MIRAI-Selete), Arifin T.Putra (Univ. of Tokyo), Akio Nishida, Shiro Kamohara (/MIRAI-Selete) SDM2008-135 ICD2008-45 |
The variability is one of the most critical issues for further miniaturization of MOS transistors. Although the variabi... [more] | SDM2008-135 ICD2008-45 pp.41-46 |
| ICD, SDM | 2006-08-18 15:25 |
Hokkaido | Hokkaido University | Impact of Random Telegraph Signals on Scaling of Multilevel Flash Memories Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago (Hitachi), Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya (Renesas) |
This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegra... [more] | SDM2006-153 ICD2006-107 pp.161-166 |
| ICD | 2005-04-15 14:00 |
Fukuoka | Analysys of SRAM neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-BipolarFailure Modes Kenichi Osada (Hitachi), Naoki Kitai (Hitachi ULSI), Shiro Kamohara (Renesas), Takayuki Kawahara (Hitachi) |
This paper describes an investigation of the upsetting of values in cells hit by alpha particles or neutrons, in which t... [more] | ICD2005-18 pp.31-36 |
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