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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2007-04-12 13:00 |
Oita | [Invited Talk]
2-Mb SPRAM (SPin-transfer torque RAM) with Bit-by-bit Bi-Directional Current Write and Parallelizing-Direction Current Read Riichiro Takemura, Takayuki Kawahara, Katsuya Miura (Hitachi), Jun Hayakawa (Hitachi/Tohoku Univ.), Shoji Ikeda, Young Min LEE, Ryutaro Sasaki (Tohoku Univ.), Yasushi Goto, Kenchi Ito (Hitachi), Toshiyasu Meguro, Fumihiro Matsukura (Tohoku Univ.), Hiromasa Takahashi (Hitachi/Tohoku Univ.), Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.)  ICD2007-6 |
A 1.8-V 2-Mb SPRAM (SPin-transfer torque RAM) chip using 0.2 µm logic process with MgO tunneling barrier cell demo... [more] | ICD2007-6 pp.29-34 |
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| ICD | 2006-04-13 10:45 |
Oita | Oita University | [Special Invited Talk]
Sub-1V DRAM Design Takayuki Kawahara (Hitachi Central Research Lab.) |
Issues for sub-1V DRAM operation and its solutions are described. Since the low voltage operation of DRAM is difficult,... [more] | ICD2006-4 pp.19-24 |
| ICD | 2006-04-13 16:40 |
Oita | Oita University | [Panel Discussion]
What is your urgent task in R/D of new embedded memories? Hideto Hidaka (Renesas), Masao Taguchi (SPANSION), Takayuki Kawahara (Hitachi), Daisaburo Takashima (Toshiba), Shuichi Ueno (Renesas), Masashi Takata (Kanazawa Univ.), Masafumi Takahashi (Toshiba) |
Recent advent of emerging memory devices circa 2000 has seen discussions directed mainly to stand-alone memory applicati... [more] | ICD2006-9 p.49 |
| ICD, ITE-CE | 2006-01-26 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Phase Change RAM Operated with 1.5-V CMOS as Low Cost Embedded Memory Satoru Hanzawa, Kenichi Osada, Takayuki Kawahara, Riichiro Takemura (Hitachi CRL), Naoki Kitai (Hitachi ULSI), Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi (Hitachi CRL), Hiroshi Moriya (Hitachi MERL), Masahiro Moniwa (Renesas) |
This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, u... [more] | ICD2005-206 pp.7-12 |
| ICD, SDM | 2005-08-18 09:20 |
Hokkaido | HAKODATE KOKUSAI HOTEL | TIS Locking Circuit for Compensating LSI Performance by Temperature Variation Goichi Ono, Masayuki Miyazaki, Kazuki Watanabe, Takayuki Kawahara (Hitachi, Ltd.) |
(Advance abstract in Japanese is available) [more] | SDM2005-130 ICD2005-69 pp.13-18 |
| ICD, SDM | 2005-08-19 13:50 |
Hokkaido | HAKODATE KOKUSAI HOTEL | A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi) |
We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operat... [more] | SDM2005-152 ICD2005-91 pp.55-60 |
| ICD | 2005-04-14 09:30 |
Fukuoka | Low-Power Embedded SRAM Modules with Expanded Margins for Writing Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) |
The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SR... [more] | ICD2005-2 pp.7-12 |
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| ICD | 2005-04-14 14:30 |
Fukuoka | [Invited Talk]
Statistical Integration In Multigigabit DRAM Design Tomonori Sekiguchi, Satoru Akiyama (Hitachi), Kazuhiko Kajigaya (Elpida), Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara (Hitachi) |
Concordant memory-array design incorporates device fluctuations statistically into signal-to-noise ratio analysis in DRA... [more] | ICD2005-8 pp.37-42 |
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| ICD | 2005-04-15 14:00 |
Fukuoka | Analysys of SRAM neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-BipolarFailure Modes Kenichi Osada (Hitachi), Naoki Kitai (Hitachi ULSI), Shiro Kamohara (Renesas), Takayuki Kawahara (Hitachi) |
This paper describes an investigation of the upsetting of values in cells hit by alpha particles or neutrons, in which t... [more] | ICD2005-18 pp.31-36 |
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| ICD | 2004-12-16 10:00 |
Hiroshima | Dynamic-Vth, Dual-Power-Supply SRAM Cell Using D2G-SOI for Low-Power SoC Application Masanao Yamaoka, Kenichi Osada, Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara (Hitachi, Ltd.) |
We developped two SRAM memory cells suitable for low-power SoC. The memory cells are composed of new FD-SOI transistors,... [more] | ICD2004-183 pp.1-5 |
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