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Committee Date Time Place Paper Title / Authors Abstract Paper #
NC, NLP 2023-01-28
16:20		 Hokkaido Future University Hakodate
(Primary: On-site, Secondary: Online)		 The boredom and electroencephalography induced during 1-back working-memory task
Yoshiaki Tsutsumi, Kiyohisa Natsume (KIT) NLP2022-93 NC2022-77		 Boredom is an emotion that arises when a simple task is performed repeatedly. People who are easily bored have been foun... [more] NLP2022-93 NC2022-77
pp.64-69
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-30
14:35		 Fukuoka Kyushu University A case study of efficient task scheduling for FPGA-based partially reconfigurable systems
Yoshiaki Tsutsumi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-43		 Dynamic Recon gurable system is the system that can build any function with recon gurable device such as FPGA (Field Pro... [more] RECONF2010-43
pp.25-30
RECONF 2010-05-13
16:20		 Nagasaki   A Case Study of Evaluation Technique for Soft Error Tolerance on SRAMs-based FPGAs.
Tsuyoshi Kimura, Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-7		 SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU),which is induced by radia... [more] RECONF2010-7
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2009-12-03
13:25		 Kochi Kochi City Culture-Plaza A Case Study of Error Correction Technique for SRAM-based FPGA using the Partial Reconfiguration
Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-41		 The present paper describes an error correction technique for SRAM-based Field Programmable Gate Arrays (FPGAs) using th... [more] RECONF2009-41
pp.1-6
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