Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC |
2024-02-28 13:40 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Test Point Selection Method for Multi-Cycle BIST Using Deep Reinforcement Learning Kohei Shiotani, Tatsuya Nishikawa, Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2023-98 |
Multi-cycle BIST is a test method that performs multiple captures for each scan pattern, proving effective in reducing t... [more] |
DC2023-98 pp.23-28 |
R |
2021-05-28 13:00 |
Online |
Online |
[Invited Talk]
Design for Testability for the Automotive Systems Hiroshi Takahashi (Ehime Univ.) |
(To be available after the conference date) [more] |
|
DC |
2020-02-26 11:35 |
Tokyo |
|
Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing Tomoki Aono, Norihiro Nakaoka, Shyu Saikou, Wang Senling, Higami Yoshinobu, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Youichi Maeda, Jun Matsushima (Renesas) DC2019-89 |
For guaranteeing the functional safety of an in-vehicle system, a power-on self-test (POST) is required to test the devi... [more] |
DC2019-89 pp.19-24 |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:10 |
Ehime |
Ehime Prefecture Gender Equality Center |
Analysis of Fault Detection Degradation Issue in Multi-cycle Test Scheme using Probabilistic Evaluation Method Norihiro Nakaoka, Tomoki Aono, Sohshi Kudoh, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) VLD2019-45 DC2019-69 |
In order to ensure the functional safety of advanced autonomous driving systems, a power-on self-test
(POST) is require... [more] |
VLD2019-45 DC2019-69 pp.145-150 |
DC |
2019-02-27 14:05 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
FF Toggle Control Point Selection Methods for Fault Detection Enhancement under Multi-cycle Testing Tomoki Aono, Hanan T.Al-Awadhi, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) DC2018-79 |
Multi-cycle Test is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power... [more] |
DC2018-79 pp.49-54 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:25 |
Hiroshima |
Satellite Campus Hiroshima |
Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT) VLD2018-57 DC2018-43 |
Scan-based logic BIST has a crucial problem of high test power dissipation. Its solution requires a flexible test power ... [more] |
VLD2018-57 DC2018-43 pp.125-130 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:00 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech) VLD2017-41 DC2017-47 |
A logic BIST scheme using multi-cycle test with partial observation has been proposed. In the scheme, the selection of f... [more] |
VLD2017-41 DC2017-47 pp.85-90 |
DC |
2014-06-20 14:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-13 |
Voltage drop by a momentary current change during capture cycles in scan-based testing brings an increase in path delay ... [more] |
DC2014-13 pp.21-26 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:55 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
A Scan-Out Power Reduction Method for Multi-Cycle BIST Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech) VLD2012-102 DC2012-68 |
Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on sc... [more] |
VLD2012-102 DC2012-68 pp.249-254 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:05 |
Miyazaki |
NewWelCity Miyazaki |
Capture power reduction in multi-cycle test structure Hisato Yamaguchi, Makoto Matsuzono, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) VLD2011-83 DC2011-59 |
Power consumption during Built-In Self-Test(BIST) is far larger than that of normal operation. Therefore, it may lead to... [more] |
VLD2011-83 DC2011-59 pp.179-183 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 15:25 |
Fukuoka |
Kyushu University |
Evaluation of Multi-Cycle Test with Partial Observation in Scan BIST Structure Hisato Yamaguchi, Makoto Matsuzono, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech./JST) VLD2010-61 DC2010-28 |
Reducing test data volume is important for field BIST because the data should be stored on a chip. In this paper, for th... [more] |
VLD2010-61 DC2010-28 pp.31-36 |