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Committee Date Time Place Paper Title / Authors Abstract Paper #
IT 2023-08-04
11:25		 Kanagawa Shonan Institute of Technology (Kanagawa, Online)
(Primary: On-site, Secondary: Online)		 Constructing Visual Cryptography Schemes for Multiple Images Using SAT Technology
Tako Hiroaki (Univ. Yamanashi), Xiao-Nan Lu (Gifu Univ.), Nabeshima Hidetomo (Univ. Yamanashi) IT2023-25		 The visual cryptography scheme (VCS) is a type of secret sharing scheme for images.The VCS uses matrices called basis ma... [more] IT2023-25
pp.62-67
MSS, CAS, SIP, VLD 2015-06-17
11:10		 Hokkaido Otaru University of Commerce (Hokkaido) Accelerating techniques for test pattern compaction for large circuits
Yusuke Matsunaga (Kyushu Univ.) CAS2015-5 VLD2015-12 SIP2015-36 MSS2015-5		 This paper presents accelerating techniques for test pattern compaction algorithm applicable for
large scale circuits.... [more]		 CAS2015-5 VLD2015-12 SIP2015-36 MSS2015-5
pp.25-30
DC 2013-02-13
10:25		 Tokyo Kikai-Shinko-Kaikan Bldg. (Tokyo) Accelerating techniques for SAT-based test pattern generation
Yusuke Matsunaga (Kyushu Univ.) DC2012-81		 A naive way to solve ATPG problem using SAT solver is to formulate a test generation problem for a fault at a time.
Thi... [more]		 DC2012-81
pp.7-12
VLD 2009-03-12
10:30		 Okinawa   (Okinawa) A Formal Verification Method for On-Chip Programmable Interconnect
Takaaki Tagawa, Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2008-142		 As the development cost increases, programmable devices such as FPGAs are becoming critically important. A key componen... [more] VLD2008-142
pp.95-100
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