Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
IPSJ-SLDM, RECONF, VLD [detail] |
2023-01-23 10:55 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80 |
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] |
VLD2022-57 RECONF2022-80 pp.7-12 |
RECONF |
2016-05-19 14:15 |
Kanagawa |
FUJITSU LAB. |
Efficiency Execution of Split Circuit in a Scalable Hardware System by Signal Compression Yoshio Murata, Hironari Yoshiuchi, Hironori Nakajo (TUAT) RECONF2016-8 |
(To be available after the conference date) [more] |
RECONF2016-8 pp.35-40 |
CPSY, DC (Joint) |
2014-07-29 09:00 |
Niigata |
Toki Messe, Niigata |
Verification Method of the Split Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism Kazuya Matsuda (TAT), Takefumi Miyoshi (e-trees.Japan), Masashi Takemoto (TAT), Satoshi Funada (e-trees.Japan), Hironori Nakajo (TAT) CPSY2014-17 |
In recent years, a high-level synthesis tool has been attracted in designing hardware circuits instead of traditional HD... [more] |
CPSY2014-17 pp.43-48 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 10:25 |
Kanagawa |
Hiyoshi Campus, Keio University |
A Storing and Regenerating Signal Information in a Scalable Hardware System Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech) VLD2013-106 CPSY2013-77 RECONF2013-60 |
In implementing a large-scale circuit into a single LSI, limitation of circuit area or degradation of maximum operating ... [more] |
VLD2013-106 CPSY2013-77 RECONF2013-60 pp.25-30 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-28 10:50 |
Kanagawa |
Hiyoshi Campus, Keio University |
Hardware Expansion Protocol in a Scalable Hardware System Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) VLD2013-107 CPSY2013-78 RECONF2013-61 |
Recently hardware acceleration with using an FPGA are focused as well as prototyping an ASIC with it. The available numb... [more] |
VLD2013-107 CPSY2013-78 RECONF2013-61 pp.31-36 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 10:30 |
Kagoshima |
|
A circuit division method for High-Level synthesis on Multi-FPGA systems in stream processing Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2013-68 |
High-Level Synthesis (HLS) has been utilized as a practical tool especially for designing Field Programmable
Gate Array... [more] |
CPSY2013-68 pp.53-58 |
RECONF |
2013-05-21 10:10 |
Kochi |
Kochi Prefectural Culture Hall |
Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-10 |
Recently, development period of ASIC is longer becouse of the increase in circuit scale.
Verification process accounts ... [more] |
RECONF2013-10 pp.49-54 |
DC, CPSY (Joint) |
2012-08-03 09:00 |
Tottori |
Torigin Bunka Kaikan |
Implementation of the circuit division for High-Level Synthesis Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2012-18 |
High-Level Synthesis has been researched and developed for these 20
years. Not only ASIC, but also reconfigurable devic... [more] |
CPSY2012-18 pp.55-60 |
IPSJ-SLDM, VLD, CPSY, RECONF [detail] |
2010-01-27 11:15 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Expansion of Hardware in a Scalable FPGA System Hironori Nakajo (Tokyo Univ. of Agr and Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech.), Satoshi Funada (e-trees.Japan, Inc), Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.) VLD2009-89 CPSY2009-71 RECONF2009-74 |
Currently, in a field of high performance computing, some FPGAs are utilized to accelerate processing against some forma... [more] |
VLD2009-89 CPSY2009-71 RECONF2009-74 pp.125-130 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 14:45 |
Kochi |
Kochi City Culture-Plaza |
Protocol for Expansion of Hardware in a Scalable FPGA System Hironori Nakajo, Ryuichi Sakamoto, Shinobu Miwa (TUAT) |
In this presentation, we have proposed a mechanism to expand hardware in the Scalable FPGA system which has been current... [more] |
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