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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NS, NWS (Joint) |
2024-01-26 11:20 |
Hiroshima | Higashisenda Campus, HiroshimaUniversity + Online (Primary: On-site, Secondary: Online) |
Tiny Message Buffers for Real CNFs
-- Towards Extreme Cache Efficiency -- Ayuto Yamada, Ryota Kawashima (NITech), Hiroki Nakayama, Tsunemasa Hayashi (BOSCO), Hiroshi Matsuo (NITech)  NS2023-170 |
The basic packet forwarding efficiency of Cloud Native Network Functions (CNFs) exceeds 100 Mpps under ideal conditions. T... [more] | NS2023-170 pp.61-66 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-15 15:55 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Preliminary Data-Pattern Analysis towards Energy-Efficient Adaptive In-Cache Computing for CNN Accelerations Zhengpan Fei, Koji Inoue (Kyushu Univ.) VLD2023-42 ICD2023-50 DC2023-49 RECONF2023-45 |
In Look-Up Table (LUT) based computing, naively covering all possible results requires an exponential amount of hardware... [more] | VLD2023-42 ICD2023-50 DC2023-49 RECONF2023-45 pp.70-75 |
| NS | 2023-10-05 09:45 |
Hokkaido | Hokkaidou University + Online (Primary: On-site, Secondary: Online) |
[Encouragement Talk]
Performance Evaluation of D2D Caching Method Using LSTM Considering Missing Data Makoto Tsunekiyo (Fukuoka Univ.), Noriaki Kamiyama (Ritsumeikan Univ.) NS2023-85 |
As video viewing on mobile terminals becomes more common, there is concern that the backhaul traffic load on cellular ne... [more] | NS2023-85 pp.77-82 |
| IN, NS (Joint) |
2023-03-02 10:00 |
Okinawa | Okinawa Convention Centre + Online (Primary: On-site, Secondary: Online) |
Performance Evaluation of D2D Caching Method Using LSTM Makoto Tsunekiyo (Fukuoka Univ.), Noriaki Kamiyama (Ritsumeikan Univ.) NS2022-175 |
As video viewing on mobile terminals becomes more common, there is concern that the backhaul traffic load on cellular ne... [more] | NS2022-175 pp.47-52 |
| HWS, VLD | 2023-03-02 16:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Reducing Conflict Misses with Multiple Indexings in Compressed Caches Tasuku Fukami, Shinya Takamaeda (UTokyo) VLD2022-98 HWS2022-69 |
Cache memory is a common hardware mechanism that improves memory access performance. To enlarge cache capacity virtually... [more] | VLD2022-98 HWS2022-69 pp.131-136 |
| ICM | 2022-07-08 10:20 |
Hokkaido | Tokachi Plaza (Primary: On-site, Secondary: Online) |
[Encouragement Talk]
Comprehensive Evaluation to Determine Cache Action in vhost-user Daichi Takeya, Ryota Kawashima (NITech), Hiroki Nakayama, Tsunemasa Hayashi (BOSCO), Hiroshi Matsuo (NITech) ICM2022-18 |
Next generation network functions are expected to be deployed on highly advanced infrastrucures towards AI-based autonom... [more] | ICM2022-18 pp.42-47 |
| RECONF | 2022-06-08 09:20 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Investigation of methods to accelerate inference processing by deep learning Seiya Iwamoto, Chikako Nakanishi (OIT) RECONF2022-13 |
AI technologies such as deep learning are generally computationally intensive and have very high performance requirement... [more] | RECONF2022-13 pp.52-56 |
| RCS, SIP, IT | 2022-01-20 10:55 |
Online | Online | Design of Coded Caching for Multi-User MISO Channels with Heterogeneous Cache Sizes Ayaka Urabe, Koji Ishibashi (UEC), MohammadJavad Salehi, Antti Tolli (Univ. Oulu) IT2021-38 SIP2021-46 RCS2021-206 |
This paper focuses on coded caching when every user has a different memory size for caching and studies the design over ... [more] | IT2021-38 SIP2021-46 RCS2021-206 pp.57-62 |
| NS | 2021-05-13 15:15 |
Online | Online | Graph Reordering while Acquiring Graph Data Managed Distributedly by Random Walk Kohei Tsuchida, Kunitake Kaneko (Keio Univ.) NS2021-20 |
It is known that cache misses occur so many times, which leads to slow down the calculation speed while graph processing... [more] | NS2021-20 pp.32-37 |
| CNR | 2020-09-24 13:40 |
Online | Online | CNR2020-3 |
(To be available after the conference date) [more] | CNR2020-3 pp.13-18 |
| VLD, IPSJ-SLDM | 2018-05-16 15:00 |
Fukuoka | Kitakyushu International Conference Center | Non-volatile Power Gating for Data Cache with Dynamic Line-selection Sosuke Akiba, Kimiyoshi Usami (SIT) VLD2018-2 |
In the whole of CPU, the proportion of energy consumption of the cache is increasing. Non-volatile Power Gating(NVPG) is... [more] | VLD2018-2 pp.19-24 |
| CQ | 2017-07-27 09:30 |
Hyogo | Kobe University | On-line flow aggregation of Internet traffic Takanori Kudo, Kazuhide Yoshikawa (Setsunan Univ.) CQ2017-29 |
We consider an on-line flow aggregation of Internet traffic using cache algorithms on limited memory. We propose an alg... [more] |
CQ2017-29 pp.1-5 |
| VLD | 2017-03-01 14:00 |
Okinawa | Okinawa Seinen Kaikan | Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines Shota Enokido, Kimiyoshi Usami (SIT) VLD2016-102 |
Non-volatile Power Gating(NVPG) is a technique to power gate memory elements to reduce leakage power while keeping the s... [more] | VLD2016-102 pp.1-6 |
| CAS, CS | 2017-02-24 13:25 |
Shiga | Improving the Performance of an SSD Cache Server Transferring Data Directly from Storage to Network Takahiro Yamaura, Haruhiko Akiyama, Eimi Murakami, Tatsuya Sasaki, Shingo Tanaka, Masataka Goto (Toshiba) CAS2016-130 CS2016-91 |
Memory cache servers leveraging SSD have been proposed to enlarge the capacity. This paper porposes a performance improv... [more] | CAS2016-130 CS2016-91 pp.89-94 |
|
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-09 10:30 |
Nagano | Kissei-Bunka-Hall (Matsumoto) | High Performance of Cache by Dynamic Control to Area Division Maika Tone, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo (Mie Univ.) CPSY2016-19 |
Today, multi-core processor is widely used to improve performance of a processor. However, memory access frequency of m... [more] |
CPSY2016-19 pp.119-124 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.) CPSY2015-72 |
Current CPU utilizes cache memory for decreasing an access speed gap between CPU and main memory. But the cache occupie... [more] |
CPSY2015-72 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement Junya Goto, Nagisa Ishiura (K.G.) VLD2015-74 DC2015-70 |
This article proposes a method of reducing cache misses on an instruction memory by inserting offsets before basic block... [more] | VLD2015-74 DC2015-70 pp.237-241 |
| ICD, IE, VLD, IPSJ-SLDM [detail] | 2015-10-26 15:25 |
Miyagi | A Power-Efficient Memory Hierarchy Design for the 3D Integration Era Wataru Uno, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.) VLD2015-30 ICD2015-43 IE2015-65 |
3D-stacked memories are expected to play key roles to realize high-performance and low-power computing systems. This pap... [more] | VLD2015-30 ICD2015-43 IE2015-65 pp.19-24 |
|
| RECONF | 2015-06-20 09:55 |
Kyoto | Kyoto University | A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications Vu Hoang Gia, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) RECONF2015-15 |
Memory latency is the most serious design concern in computing centric architectures integrated with cache levels as a d... [more] | RECONF2015-15 pp.79-84 |
| DC, CPSY | 2015-04-17 13:00 |
Tokyo | CGRA in Cache for Graph Applications Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-7 DC2015-7 |
Recently, CGRA has been suggested high-speed and lower power consumption of graph processing. Generally, CGRA is connect... [more] | CPSY2015-7 DC2015-7 pp.37-41 |
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