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Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 14:15 |
Fukuoka | Kitakyushu Science and Research Park | A Method of Processing Data-Parallel Tasks on Multi-Context Reconfigurable Processor Koichi Araki, Yukinori Sato, Yasushi Inoguchi (Japan Advanced Institute of Science and Technology)  RECONF2008-41 |
A Multi-context Reconfigurable Processor (MRP) can treat various tasks with hardware. However, in the case of treating a... [more] | RECONF2008-41 pp.15-20 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 13:25 |
Fukuoka | Kitakyushu Science and Research Park | An Adaptive Pattern Recognition hardware with On-chip Dynamic and Partial Reconfiguration Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Tsukuba Univ.), Kyrre Glette, Jim Toressen (Oslo Univ.) RECONF2008-50 |
A pattern recognition system that can process a large amount of image data at high speed is required in many fields. I... [more] |
RECONF2008-50 pp.63-68 |
| ISEC | 2008-09-12 17:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | How to introduce the dynamic key to a provably Secure Block Cipher using FPGA Partial Reconfiguration Kenji Takahashi, Tetsuya Ichikawa (Mitsubishi Electric Engineering), Toru Sorimachi (Mitsubishi Electric) ISEC2008-72 |
Cipher circuits are required both to have high security and to show high performance as to circuit scale and processing ... [more] | ISEC2008-72 pp.63-68 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 14:45 |
Kanagawa | Hiyoshi Campus, Keio University | A study of the effectiveness of dynamic partial reconfiguration for size and power reduction Yohei Hori, Hirofumi Sakane, Kenji Toda (AIST) VLD2007-110 CPSY2007-53 RECONF2007-56 |
We evaluated the effectiveness of the partial reconfiguration in reducing area and power consumption of an FPGA-based ci... [more] | VLD2007-110 CPSY2007-53 RECONF2007-56 pp.31-36 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:35 |
Fukuoka | Kitakyushu International Conference Center | Development of Inter-module Communication Mechanism for Dynamically Reconfigurable System Tomoyuki Ishida, Taiichiro Yatsunami, Osamu Kawaguchi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2007-36 |
In recent years, study of Programmable Logic Device, e.g. FPGAs, is much-investigated, and the dynamic reconfigurable sy... [more] | CPSY2007-36 pp.7-12 |
| RECONF | 2007-09-21 10:00 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Dynamically Reconfigurable Protocol Transducer Synthesis for utilizing IPs Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita (Tokyo Univ.) RECONF2007-24 |
Protocol transducer synthesis is one of the most important issues for efficient IP core reuse in SoC designs. We propo... [more] |
RECONF2007-24 pp.53-58 |
| RECONF | 2005-12-02 09:30 |
Fukuoka | Kitakyushu International Conference Center | Development of a Reconfiguration Management Mechanism for Dynamically Reconfigurable System Takanori Susaki, Isao Sakamoto, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
We have developed a dynamically reconfigurable system, which uses an embedded processor FPGA. In this system, an embedde... [more] | RECONF2005-72 pp.1-6 |
| RECONF | 2005-09-15 15:00 |
Hiroshima | Development of a partial reconfiguration controller for an embedded processor FPGA Isao Sakamoto, Takanori Susaki, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
We develop dynamically reconfigurable system，named EXPRESS-2，using partially reconfigurable FPGA. The FPGA contains one ... [more] | RECONF2005-37 pp.43-48 |
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