| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD, ITE-IST [detail] | 2021-08-18 13:00 |
Online | Online | [Invited Talk]
A 12nm autonomous driving processor running 60.4 TOPS and 13.8 TOPS/W CNNs with task-separated ASIL D control Katsushige Matsubara, Lieske Hanno (Renesas Electronics), Motoki Kimura (Renesas Electronics Europe), Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei (Renesas Electronics)  SDM2021-39 ICD2021-10 |
Next-generation driver assistance systems and automated driving systems require both high performances to realize enormo... [more] | SDM2021-39 ICD2021-10 pp.48-53 |
| HWS, VLD [detail] | 2021-03-03 14:55 |
Online | Online | Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
| HWS, VLD [detail] | 2021-03-04 14:15 |
Online | Online | Experiments of Data Authenticity Verification in Multi-Node IoT Systems Using Elliptic Curve Digital Signature Chips Yuya Takahashi, Takuya Matsumaru, Kazuki Monta (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.) VLD2020-85 HWS2020-60 |
Practicality of IoT systems requires the efficiency and speed of crypto processing in edge nodes and remote servers. So ... [more] | VLD2020-85 HWS2020-60 pp.97-101 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 15:15 |
Online | Online | A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech) VLD2020-49 CPSY2020-32 RECONF2020-68 |
In recent years, CNN has been used for various tasks in the field of computer vision and has achievedexcellent performan... [more] | VLD2020-49 CPSY2020-32 RECONF2020-68 pp.58-62 |
| HWS, VLD | 2019-03-01 10:00 |
Okinawa | Okinawa Ken Seinen Kaikan | Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85 |
This paper presents a method of automatically synthesizing a hardware design from a set of source codes for a real-time... [more] |
VLD2018-122 HWS2018-85 pp.175-180 |
| RCS, AP (Joint) |
2018-11-22 11:20 |
Okinawa | Okinawa Industry Support Center | Hardware Accelerator for Coordinated Radio-Resource Scheduling in 5G Ultra-high-density Distributed Antenna Systems Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura, Satoshi Shigematsu (NTT) RCS2018-208 |
This paper presents a novel radio-resource scheduler with a hardware accelerator for coordinated scheduling in 5G ultra-... [more] | RCS2018-208 pp.173-178 |
| RECONF | 2018-09-18 14:50 |
Fukuoka | LINE Fukuoka Cafe Space | Data Flow Representation and its Applications to Machine Learning Accelerator Kazuki Nakada (Tsukuba Univ. of Tech.), Keiji Miura (Kwansei Gakuin Univ.) RECONF2018-32 |
Researches and development of machine learning accelerators have been rapidly progressing. It is becoming important to r... [more] | RECONF2018-32 pp.73-78 |
| CS | 2017-07-27 13:45 |
Nagasaki | Fukue Bunka Kaikan | [Invited Talk]
A Study on Application of Hardware Accelerator for Radio-resource Scheduler in 5G Mobile Systems Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura (NTT) CS2017-24 |
For the fifth generation mobile communication systems (5G), in order to increase overall system throughput, ultra-high-d... [more] | CS2017-24 pp.53-58 |
| RCS | 2017-06-21 16:35 |
Okinawa | Ishigaki Shoukou Kaikan | Hardware Accelerator for Radio-Resource Scheduling in Ultra-high Dense Distributed Antenna Systems Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura (NTT) RCS2017-58 |
For the fifth generation mobile communication systems (5G), in order to increase overall system throughput, ultra-high-d... [more] | RCS2017-58 pp.49-54 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 13:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis Daisuke Ishikawa, Kenshu Seto (TCU) VLD2016-69 DC2016-63 |
We propose data transfer optimization in accelerator design with high-level synthesis. Typical accelerator designs perfo... [more] | VLD2016-69 DC2016-63 pp.147-152 |
| NS | 2016-10-20 13:50 |
Hyogo | Himeji Nishi-Harima Area Jibasan Center | Distributed Packet Processing Architecture using Hardware Accelerators for 100Gbps Forwarding Throughput on Virtualized Edge Router Satoshi Nishiyama, Hitoshi Kaneko, Ichiro Kudo (NTT) NS2016-90 |
To implement virtualized service edge functions on carrier networks by general-purpose servers, it is necessary to impro... [more] | NS2016-90 pp.13-18 |
| RECONF | 2016-05-19 10:45 |
Kanagawa | FUJITSU LAB. | Design of an FPGA-based Accelerator for Moleculer Dynamics Using OpenCL Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.), Kota Kasahara (Osaka Univ.) RECONF2016-4 |
Molecular dynamics (MD) simulations are very important to study physical properties of atoms and molecules. However, a h... [more] | RECONF2016-4 pp.13-16 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-19 17:45 |
Kanagawa | Hiyoshi Campus, Keio University | FPGA-based Parallel Processing of Sliding-Window Aggregate Queries on Data Streams Yoshimitsu Ogawa, Yasin Oge, Masato Yoshimi, Celimuge Wu, Tsutomu Yoshinaga (UEC) VLD2015-86 CPSY2015-118 RECONF2015-68 |
In this report, we present an evaluation of Configurable Query Processing Hardware (CQPH) implemented on multiple FPGAs.... [more] | VLD2015-86 CPSY2015-118 RECONF2015-68 pp.79-84 |
| RECONF | 2014-06-12 15:35 |
Miyagi | Katahira Sakura Hall | Implementation of a RISC Processor with a Complex Instruction Accelerator
-- Return to a CISC -- Ryota Suzuki (Tokyo Univ. of Agriculture and Tech.), Takefumi Miyoshi (e-trees), Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) RECONF2014-13 |
In this paper, we propose a RISC processor with an accelerator which can execute a complex instruction with a co-proces... [more] |
RECONF2014-13 pp.67-72 |
| RECONF | 2014-06-12 16:25 |
Miyagi | Katahira Sakura Hall | Design of an FPGA-Based Accelerator for Shortest-Path Search over Large-Scale Graphs Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-15 |
Shortest-path search over large scale graphs plays an important role in various applications. However, shortest path alg... [more] | RECONF2014-15 pp.79-83 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 16:45 |
Kanagawa | Hiyoshi Campus, Keio University | Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-133 CPSY2013-104 RECONF2013-87 |
This article presents a method of synthesizing hardware that accelerates specified sections of binary programs. The acce... [more] | VLD2013-133 CPSY2013-104 RECONF2013-87 pp.185-190 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 14:10 |
Kagoshima | A Method and Evaluation of Dynamic Relocation for Shared Multi-FPGA System Yuta Ukon, Takuya Otsuka, Takashi Aoki, Yusuke Sekihara, Akihiko Miyazaki (NTT) VLD2013-100 DC2013-66 |
Recently, it is expected to provide high-load services such as analysis of big data or image processing in a data center... [more] | VLD2013-100 DC2013-66 pp.281-286 |
|
| EMCJ, IEE-EMC, MW, EST [detail] | 2013-10-24 15:45 |
Miyagi | Tohoku Univ. | Design of an FPGA-Based FDTD Accelerator Using OpenCL Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) EMCJ2013-73 MW2013-113 EST2013-65 |
High-performance computing systems with dedicated hardware on FPGAs can achieve power efficient computations compared wi... [more] | EMCJ2013-73 MW2013-113 EST2013-65 pp.73-76 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 16:25 |
Kanagawa | Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu Shunsuke Satake (Kwansei Gakuin Univ), Nagisa Ishiura, Shimpei Tamura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ), Hiroyuki Kanbara (ASTEM) VLD2012-119 CPSY2012-68 RECONF2012-73 |
This article presents an improvement over the hardware accelerator tightly coupled with a CPU. While the previously pr... [more] |
VLD2012-119 CPSY2012-68 RECONF2012-73 pp.69-73 |
|
| CAS | 2012-01-19 11:15 |
Fukuoka | Kyushu Univ. | [Invited Talk]
Design Methodology of Group Signature Circuits for Cloud Servers and Clients Sumio Morioka, Jun Furukawa, Yuichi Nakamura, Kazue Sako (NEC) CAS2011-90 |
Group signature is one of the main theme in recent digital signature studies. The scheme allows users to sign anonymousl... [more] | CAS2011-90 pp.31-36 |
[Return to Top Page]