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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 32  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS, ICD 2024-02-29
11:15
Okinawa
(Primary: On-site, Secondary: Online)
Design of RISC-V SoC with Post-quantum Encryption Algorithm Acceleration
Jiyuan Xin, Makoto Ikeda (UTokyo) VLD2023-110 HWS2023-70 ICD2023-99
The foundational elements of the Internet of Things (IoT) are increasingly intricate and robust Systems-on-Chips (SoCs) ... [more] VLD2023-110 HWS2023-70 ICD2023-99
pp.66-71
VLD, HWS, ICD 2024-03-01
15:30
Okinawa
(Primary: On-site, Secondary: Online)
A Pipelined NTT Transformer and its Extension Scheme Designed for the Digital Signature Scheme Crystals-Dilithium
Pengfei Sun, Makoto Ikeda (Tokyo Univ.) VLD2023-130 HWS2023-90 ICD2023-119
As quantum computing advances, it threatens the security of current encryption algorithms, making Post-Quantum Cryptogra... [more] VLD2023-130 HWS2023-90 ICD2023-119
pp.161-166
VLD, HWS, ICD 2024-03-02
10:50
Okinawa
(Primary: On-site, Secondary: Online)
Design of General Hardware for Optimal Strategy in Isogeny-Based Post-Quantum Cryptography
Kosei Nakamura, Makoto Ikeda (UT) VLD2023-137 HWS2023-97 ICD2023-126
The computation in isogeny-based post-quantum cryptography primarily consists of two operations: scalar multiplication o... [more] VLD2023-137 HWS2023-97 ICD2023-126
pp.198-203
IE, CS, IPSJ-AVM [detail] 2023-12-11
15:30
Fukuoka Kyushu Institute of Technology
(Primary: On-site, Secondary: Online)
[Special Invited Talk] High-Performance Image Processing Utilizing Hardware
Norishige Fukushima (nitech) CS2023-83 IE2023-25
High-speed image signal processing is important to realize applications in various environments.
To complete image proc... [more]
CS2023-83 IE2023-25
p.16
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2023-11-16
13:45
Kumamoto Civic Auditorium Sears Home Yume Hall
(Primary: On-site, Secondary: Online)
VLD2023-50 ICD2023-58 DC2023-57 RECONF2023-53 In stochastic computing, which is a computational method with probabilities, various one-input functions, such as absolu... [more] VLD2023-50 ICD2023-58 DC2023-57 RECONF2023-53
pp.106-111
RECONF 2023-09-14
16:10
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Building Simulation Environment for Reconfigurable Virtual Accelerator (ReVA)
Shunya Kawai, Kazuki Yaguchi, Eriko Maeda (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) RECONF2023-21
In this paper,we propose a simulation environment using Post-Implementation Simulation of Vivado to confirm functions of... [more] RECONF2023-21
pp.11-12
RECONF 2023-09-14
16:40
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism
Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-24
Vector processors can load lots of data and perform operations in parallel.
The Vector Register Sharing Mechanism, prop... [more]
RECONF2023-24
pp.18-19
RECONF 2023-09-15
13:25
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Implementation and Evaluation of a Hardware Accelerator via Vector Register Sharing Mechanism for Massive Data Transfer
Michiya Kato, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi MIyoshi (Wasarabo LLC), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-29
Vector Register Sharing Mechanism is a method of data transfer by connecting some of the vector registers in the vector ... [more] RECONF2023-29
pp.40-45
RECONF 2023-09-15
13:50
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Abstraction of Processor-FPGA Communication in Reconfigurable Virtual Accelerator (ReVA)
Eriko Maeda, Kazuki Yaguchi, Shunya Kawai, Daichi Teruya (TUAT), Yasunori Osana (Kumamoto Univ.), Takehumi Miyoshi (Wasalabo), Hironori Nakajo (TUAT) RECONF2023-30
In recent years, hardware acceleration for HPC and AI has become a challenge due to the lack of resources and the comple... [more] RECONF2023-30
pp.46-51
RECONF 2023-08-04
14:55
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
An Elastic FPGA-based Accelerator for Bayesian Network Structure Learning
Ryota Miyagi (The Univ. of Tokyo), Ryota Yasudo (Kyoto Univ.), Kentaro Sano (RIKEN), Hideki Takase (The Univ. of Tokyo) RECONF2023-15
A Bayesian network is a powerful model for representing knowledge involving uncertainty within discrete random variables... [more] RECONF2023-15
pp.7-12
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
10:55
Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA)
Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] VLD2022-57 RECONF2022-80
pp.7-12
HWS, ICD 2022-10-25
15:40
Shiga
(Primary: On-site, Secondary: Online)
Hardware Acceleration of TFHE-based Adder by Controlling Error
Yinfan Zhao, Ikeda Makoto (Univ. of Tokyo) HWS2022-40 ICD2022-32
Fully homomorphic encryption (FHE) is expected to be used in the secure delegating computation. The bootstrapping in the... [more] HWS2022-40 ICD2022-32
pp.58-63
RECONF 2022-06-07
14:50
Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)
Vector Register Sharing Mechanism for Hardware Acceleration
Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2022-5
In this paper, we present a vector register sharing mechanism that directly shares vector registers inside the processor... [more] RECONF2022-5
pp.26-31
SR 2022-05-11
15:40
Tokyo NICT Koganei
(Primary: On-site, Secondary: Online)
[Invited Lecture] vRAN Acceleration by GPU -- NVIDIA Platform and Aerial SDK --
Hashimoto Noriyuki, Noda Makoto (NVIDIA) SR2022-3
Virtualized RAN (vRAN) and Open RAN are promising technologies for the 5G and beyond 5G systems, where vRAN is composed ... [more] SR2022-3
pp.13-17
NS 2022-04-15
13:25
Tokyo kikai shinkou kaikan + online
(Primary: On-site, Secondary: Online)
Study of Multi-access VPN Systems with Hardware Accelerators
Katsuma Miyamoto, Hiroki Kano, Koji Sugisono, Shinya Kawano (NTT) NS2022-5
In recent years, the use of VPN services has increased rapidly due to the spread of telework, and the use of VPN service... [more] NS2022-5
pp.25-30
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-25
15:35
Online Online Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA)
Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT) VLD2021-72 CPSY2021-41 RECONF2021-80
In recent years, the amount of computation and data in HPC, AI, and other computational processing has become increasing... [more] VLD2021-72 CPSY2021-41 RECONF2021-80
pp.132-137
RCS, AP
(Joint)
2018-11-22
11:20
Okinawa Okinawa Industry Support Center Hardware Accelerator for Coordinated Radio-Resource Scheduling in 5G Ultra-high-density Distributed Antenna Systems
Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura, Satoshi Shigematsu (NTT) RCS2018-208
This paper presents a novel radio-resource scheduler with a hardware accelerator for coordinated scheduling in 5G ultra-... [more] RCS2018-208
pp.173-178
HWS, ICD 2018-10-29
14:30
Osaka Kobe Univ. Umeda Intelligent Laboratory An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier
Yota Okuaki, Junichi Sakamoto, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) HWS2018-50 ICD2018-42
One of the biggest problems of the emerging cyber-physical and cloud computing systems is how to ensure security with en... [more] HWS2018-50 ICD2018-42
pp.19-24
CS 2017-07-27
13:45
Nagasaki Fukue Bunka Kaikan [Invited Talk] A Study on Application of Hardware Accelerator for Radio-resource Scheduler in 5G Mobile Systems
Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura (NTT) CS2017-24
For the fifth generation mobile communication systems (5G), in order to increase overall system throughput, ultra-high-d... [more] CS2017-24
pp.53-58
RCS 2017-06-21
16:35
Okinawa Ishigaki Shoukou Kaikan Hardware Accelerator for Radio-Resource Scheduling in Ultra-high Dense Distributed Antenna Systems
Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura (NTT) RCS2017-58
For the fifth generation mobile communication systems (5G), in order to increase overall system throughput, ultra-high-d... [more] RCS2017-58
pp.49-54
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