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All Technical Committee Conferences (Searched in: Recent 10 Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
QIT (2nd) |
2021-05-24 15:30 |
Online |
Online (Online) |
[Invited Talk]
Loop-based photonic quantum computing Shuntaro Takeda (Univ. of Tokyo) |
Today quantum computers are being developed with a variety of physical systems. Photonic quantum computing is one of the... [more] |
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DC |
2018-02-20 09:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo) |
A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2017-78 |
It is required to reduce the number of test patterns to reduce test cost for VLSIs. Especially, design-for-testability m... [more] |
DC2017-78 pp.7-12 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea (Kumamoto) |
A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43 |
Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the incr... [more] |
VLD2017-37 DC2017-43 pp.61-66 |
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