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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2009)
Search Results: Keywords 'from:2009-05-20 to:2009-05-20'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, IPSJ-SLDM | 2009-05-20 14:30 |
Fukuoka | Kitakyushu International Conference Center | Task Migration for Energy Savings in Multiprocessor Real-Time Systems Gang Zeng (Nagoya Univ.), Shinpei Kato (The Univ. of Tokyo), Tetsuo Yokoyama, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)  VLD2009-1 |
A task migration method is proposed for energy savings in multiprocessor real-time systems. The method is based on the p... [more] | VLD2009-1 pp.1-6 |
| VLD, IPSJ-SLDM | 2009-05-20 14:55 |
Fukuoka | Kitakyushu International Conference Center | A Weighted-Sum Circuit Using Selector Logic By Transforming Bit-Level Operations Tomoaki Hara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Printing Corp.) VLD2009-2 |
Consider a weighted-sum operation, sum of whose weights becomes one. This operation can be applied to various image pro... [more] |
VLD2009-2 pp.7-12 |
| VLD, IPSJ-SLDM | 2009-05-20 15:20 |
Fukuoka | Kitakyushu International Conference Center | A scan test generation method to reduce the number of detected untestable faults Hiroshi Ogawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) VLD2009-3 |
There are faults which can be detected by only the invalid test patterns. This is one of the causes for the overtesting.... [more] | VLD2009-3 pp.13-18 |
| VLD, IPSJ-SLDM | 2009-05-21 10:00 |
Fukuoka | Kitakyushu International Conference Center | A RST Construction Method for Vertices with Maximum Path Length Masafumi Inoue, Yoichi Tomioka (Tokyo Inst. of Tech.), Yukihide Kohira (the Univ. of Aizu), Atsushi Takahashi (Osaka Univ.) VLD2009-4 |
As the wire width decreases, the ratio of routing delay among signal propagation delay increases and the routing delay c... [more] | VLD2009-4 pp.31-36 |
| VLD, IPSJ-SLDM | 2009-05-21 10:25 |
Fukuoka | Kitakyushu International Conference Center | Importance sampling with two-phase preprocess considering structural symmetry of SRAM circuits Takanori Date, Shiho Hagiwara, Takumi Uezono (Tokyo Inst. of Tech.), Takashi Sato (Kyoto Univ.), Kazuya Masu (Tokyo Inst. of Tech.) VLD2009-5 |
The influence of process variation on SRAM yield has become a serious consern in scaled technologies. Monte Carlo-based... [more] |
VLD2009-5 pp.37-42 |
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