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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita |
B-ConPlaza |
Scalable and Low Latency Structure for Castle of Chips Hiroshi Nakahara, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2014-79 |
Castle of Chips(CoC) is a chip stacking structure without chip-to-chip wired interconnection. Instead, each chip uses in... [more] |
CPSY2014-79 pp.39-44 |
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