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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
15:25		 Kanagawa Hiyoshi Campus, Keio University Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device
Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ) 		(To be available after the conference date) [more]
VLD 2011-09-27
09:45		 Fukushima University of Aizu Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD
Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City Univ.), Takashi Ishiguro (Taiyo Yuden) VLD2011-47		 FPGAs realize a target circuit by realizing logic cells by LUTs and connecting wires among the logic cells by switch blo... [more] VLD2011-47
pp.37-42
RECONF 2010-09-16
16:10		 Shizuoka Shizuoka University (Faculty of Eng., Hall 2) An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs
Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN) RECONF2010-26		  [more] RECONF2010-26
pp.49-54
MBE 2009-01-24
13:15		 Saga Saga University [Special Talk] Development of Automatic Integrative EEG Interpretation System -- A Long-Term Collaboration between Medical and Engineering Fields --
Masatoshi Nakamura (Saga Univ.) MBE2008-89		 Integrative EEG (electroencephalogram) interpretation requires an enough skill and hard task for EEGers’ (eletroencephal... [more] MBE2008-89
pp.67-72
ICD, VLD 2007-03-08
16:10		 Okinawa Mielparque Okinawa Programmable CMOS Analog Circuit with Body Biasing
Youhei Ide, Toru Fujimura, Shinya Takeshita, Masatoshi Nakamura, Shigetoshi Nakatake (Univ. of Kitakyushu) 		 [more] VLD2006-137 ICD2006-228
pp.109-114
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