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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ED 2009-06-24
15:15		 Overseas Haeundae Grand Hotel, Busan, Korea Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-end Metal Line of CMOS Circuits
Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda (Tohoku Univ.), Katsuya Miura (Tohoku Univ./Hitachi), Jun Hayakawa (Hitachi), Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ED2009-53 SDM2009-48		 In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrat... [more] ED2009-53 SDM2009-48
pp.13-16
SDM 2007-03-15
13:30		 Tokyo Kikai-Shinko-Kaikan Bldg. Reset switching mechanism of ReRAM using thermal reaction model
Yoshihiro Sato, Kentaro Kinoshita, Hideyuki Noshiro, Masaki Aoki, Yoshihiro Sugiyama (FUJITSU LAB.) 		We investigated the resistive memory (ReRAM) cells with binary metal oxide (BMO) junctions by applying a short voltage p... [more] SDM2006-255
pp.7-10
ICD 2005-04-15
10:30		 Fukuoka   A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture
Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy) 		A 1Mbit MRAM with a 0.81um2 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) cell using 0.13um 4LM logic technology has... [more] ICD2005-13
pp.1-6
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