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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2016-03-01
11:20		 Okinawa Okinawa Seinen Kaikan Timing-error-tolerant AES Cipher
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-123		 With the technologies advance, the importance of crypto circuits is increasing as well. AES cipher is well known as theo... [more] VLD2015-123
pp.73-78
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
10:05		 Oita B-ConPlaza An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-81 DC2014-35		 As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error cor... [more] VLD2014-81 DC2014-35
pp.57-62
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