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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SIP, IE, IPSJ-SLDM 2006-10-26
11:50
Miyagi   Reducing the Circuit Size of Multipliers
Tan Jiunn Jong Edwin, Ryusuke Egawa (GSIS Tohoku University), Jubee Tada (Faculty of Engineering, Yamagata University), Kenichi Suzuki (GSIS Tohoku University), Gensuke Goto (Faculty of Engineering, Yamagata University), Tadao Nakamura (GSIS Tohoku University)
Aiming at reducing the power consumption of future VLSIs, a small and fast arithmetic unit is required. Since multiplier... [more] SIP2006-91 ICD2006-117 IE2006-69
pp.45-50
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