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Committee Date Time Place Paper Title / Authors Abstract Paper #
EMCJ, IEE-EMC 2011-06-24
14:00		 Kyoto Kyoto Univ. Fast Simulation Technique Based on Block-Latency Insertion Method for Large Linear Circuit with CMOS Inverters
Yusuke Hizawa, Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) EMCJ2011-40		 For an analysis of large networks including nonlinear active devices and coupled elements, conventional SPICE-like simul... [more] EMCJ2011-40
pp.37-42
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