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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2013-04-11 17:30 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Panel Discussion]
Future prospects of memory solutions for smart society
-- Can new nonvolatile memories replace SRAM/DRAM/Flash? -- Koji Nii (Renesas Erctronics), Tetsuo Endoh (Tohoku Univ.), Yoshikazu Katoh (Panasonic), Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (Elpida Memory), Atsushi Kawasumi (Toshiba), Toru Miwa (SanDisk)  ICD2013-11 |
(To be available after the conference date) [more] | ICD2013-11 p.53 |
| ICD | 2010-04-23 11:25 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
High-Speed Memory Interfaces
-- DDR/GDDR-DRAM -- Yasuhiro Takai (Elpida) ICD2010-15 |
(To be available after the conference date) [more] | ICD2010-15 pp.81-82 |
| ICD | 2008-04-17 15:20 |
Tokyo | [Panel Discussion]
Probing into the Potential of the Future Flash
-- An Impact of Flash Revolution -- Kazuhiko Kajigaya (Elpida), Naoharu Shinozaki (Spansion), Toshio Kakihara (HGST), Kazushige Kanda (Toshiba), Michio Kobayashi (Spansion), Makoto Saen (Hitachi), Tadahiko Sugibayashi (NEC), Ken Takeuchi (Tokyo Univ.), Hisao Tsukazawa (Toshiba) ICD2008-7 |
Flash-memory is now the driving force for the semiconductor process technology and trying to expand its new market with ... [more] | ICD2008-7 pp.37-38 |
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| CPM, ICD | 2008-01-18 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg | A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board that Simulates Memory Module Yutaka Uematsu, Hideki Osaka (Hitachi), Yoji Nishio, Susumu Hatano (Elpida) CPM2007-139 ICD2007-150 |
Aiming to achieve double data rate-synchronous DRAM (DDR-SDRAM) at low-cost and with high noise tolerance by setting ade... [more] | CPM2007-139 ICD2007-150 pp.65-69 |
| ICD, SDM | 2006-08-17 16:35 |
Hokkaido | Hokkaido University | 17GHz Fine Grid Clock Distribution with Uniform-Amplitude Standing-Wave Oscillator Atsushi Mori, Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Iwata (Hiroshima Univ.), Hiroaki Ikeda (Elpida) |
[more] | SDM2006-139 ICD2006-93 pp.81-85 |
| SDM | 2006-06-21 13:50 |
Hiroshima | Faculty Club, Hiroshima Univ. | Characterization of Interfacial Reactions in Al2O3/SiNx/poly-Si Stack Structure by Photoemission Measurements Hiroaki Furukawa, Masahiro Taira, Akio Ohta, Hiroshi Nakagawa, Hideki Murakami, Seiichi Miyazaki (Hiroshima Univ.), Kenji Komeda, Mitsuhiro Horikawa, Kuniaki Koyama, Hideharu Miyake (Elpida Memory) |
[more] | SDM2006-44 pp.13-17 |
| ICD | 2006-04-13 09:20 |
Oita | Oita University | The Origin of Variable Retention Time in DRAM
-- Fluctuation of Junction Leakage -- Yuki Mori (Hitachi CRL), Kiyonori Ohyu, Kensuke Okonogi (Elpida), Renichi Yamada (Hitachi CRL) |
[more] | ICD2006-1 pp.1-6 |
| ICD | 2006-04-13 10:10 |
Oita | Oita University | An 8.4ns Column-Access 1.6Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme Shuichi Kubouchi (Hitachi ULSI), Hiroki Fujisawa, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda (Elpida Memory), Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka (Hitachi ULSI), Masayuki Nakamura (Elpida Memory) |
The column access time of a 512Mb DDR3 SDRAM made by a 90nm dual-gate CMOS process is reduced by 2.9ns to 8.4ns through ... [more] | ICD2006-3 pp.13-18 |
| ICD, CPM | 2005-09-08 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Development of Design Techniques for Semiconductor-Package By using Simplified DRAM Macro Model of Power System Satoshi Nakamura, Takashi Suga (Hitachi PERL), Mitsuaki Katagiri, Yoji Nishio, Seiji Funaba, Yukitoshi Hirose, イサ サトシ (Elpida) |
In late years, MCP(Multi Chip Package) and SiP(System in Package) which has plural semiconductor chips in one package be... [more] | CPM2005-87 ICD2005-97 pp.13-18 |
| ICD, SDM | 2005-08-19 13:50 |
Hokkaido | HAKODATE KOKUSAI HOTEL | A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi) |
We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operat... [more] | SDM2005-152 ICD2005-91 pp.55-60 |
| ICD | 2005-04-14 14:30 |
Fukuoka | [Invited Talk]
Statistical Integration In Multigigabit DRAM Design Tomonori Sekiguchi, Satoru Akiyama (Hitachi), Kazuhiko Kajigaya (Elpida), Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara (Hitachi) |
Concordant memory-array design incorporates device fluctuations statistically into signal-to-noise ratio analysis in DRA... [more] | ICD2005-8 pp.37-42 |
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| ICD | 2005-04-14 19:00 |
Fukuoka | * Katsuyuki Sato (Elpida), Hiroyuki Yamauchi (Matsushita), Kenji Numata (Toshiba), Takashi Akazawa (Renesas), Yasunao Katayama (IBM Japan) |
[more] | ICD2005-12 p.59 |
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| ICD | 2004-12-16 13:00 |
Hiroshima | [Invited Talk]
DRAM Architecture Trend
-- DRAM Architecture Variation in relation to System Requirements -- Manabu Ando (Elpida) |
[more] | ICD2004-187 pp.25-30 |
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