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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
17:00
Kanagawa   Fast Solution of Link Disjoint Path Algorithm on Parallel Reconfigurable Processor DAPDNA-2
Taku Kihara, Sho Shimizu, Shan Gao, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Akifumi Watanabe (IPFlex) VLD2008-125 CPSY2008-87 RECONF2008-89
In next generation network, a high level reliabilty is strong required. In a protection, which is the one of network sur... [more] VLD2008-125 CPSY2008-87 RECONF2008-89
pp.201-206
PN, NS
(Joint)
2008-12-18
11:20
Hyogo Koube Univ. Network Reconfigure Algorithm With Least Resource For Energy Efficient Optical Network
Aya Tsurusaki, Yutaka Arakawa, Daisuke Ishii, Naoaki Yamanaka, Hiroyuki Ishikawa (Keio Univ.), Yasuhiro Shiba (IPFlex Inc.) PN2008-32
The Internet has been popular recently, and network traffic of the Inter net is growing. The power
consumpution is an i... [more]
PN2008-32
pp.1-5
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-18
13:50
Fukuoka Kitakyushu Science and Research Park A Novel Network Optimization Method using On-Chip Virtual Network on Dynamically Reconfigurable Processor DAPDNA-2
Shan Gao, Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio University), Kosuke Shiba (IPFlex Inc) RECONF2008-51
 [more] RECONF2008-51
pp.69-74
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-18
14:55
Fukuoka Kitakyushu Science and Research Park The Experiment of Automatic circuit generation for image processing using extended C code on DRP -- DFC, the Language of Hardware generation for DAPDNA - its issue and solution --
Kazuo Yamada, Takao Naito (Fuji Xerox), Mitsumasa Yoshimura, Jiro Iwai (IPFlex) RECONF2008-53
 [more] RECONF2008-53
pp.81-86
PN 2008-08-08
10:20
Hokkaido Asari Classe Hotel Network Reconfigure Algorithm for Power Consumption
Yutaka Arakawa, Daisuke Ishii, Aya Tsurusaki, Naoaki Yamanaka, Hiroyuki Ishikawa (Keio Univ.), Kousuke Shiba (IPFlex) PN2008-16
New network reconfigure algorithm for low power consumption is proposed. Network is used minimum set of node and link wh... [more] PN2008-16
pp.13-18
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-16
17:25
Kanagawa Hiyoshi Campus, Keio University Fast solution method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2
Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex) VLD2007-116 CPSY2007-59 RECONF2007-62
This paper proposes a fast calculation method of the set cover problem, which is implemented on reconfigurable processor... [more] VLD2007-116 CPSY2007-59 RECONF2007-62
pp.67-72
IN, NS
(Joint)
2006-03-02
09:50
Okinawa Rizzan Sea-Park Hotel Tancha-Bay (Okinawa) Shortest path algorithm on parallel reconfigurable processor DAPDNA
Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex)
 [more] NS2005-162
pp.17-20
RECONF 2005-11-30
16:10
Fukuoka Kitakyushu International Conference Center Implementation of 1-D/2-D FFT on the Dynamically Reconfigurable Processor DAPDNA-2
Kosuke Shiba, Atsushi Imaizumi, Takeshi Sakuma (IPFlex)
The Fast Fourier Transform (FFT), which is applied to extensive fields as a basic technology of various digital signal p... [more] RECONF2005-56
pp.19-24
RECONF 2005-12-01
09:30
Fukuoka Kitakyushu International Conference Center A Study on Shortest Path Routing Algorithm on Reconfigurable Processor
Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex)
n IP networks, we ordinally use OSPF(Open Shortest Path First) as a routing protocol. OSPF find the shortest path using ... [more] RECONF2005-59
pp.1-6
 Results 1 - 9 of 9  /   
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