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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY 2008-10-31
11:15
Hiroshima Hiroshima City Univ. [Special Invited Talk] The Proposal of the MPLD Architecture for High Performance Computing
Tetsuo Hironaka, Naoki Hirakawa (Hiroshima City Univ.), Masanori Yoshihara (Hiroshima City Univ./Renesas Technorogy Corp.), Kazuya Tanigawa (Hiroshima City Univ.), Masayuki Sato (Taiyo Yuden Co., Ltd.) CPSY2008-31
As the practical use of high performance FPGA increases, research on using FPGAs in the field of HPC (High Performance C... [more] CPSY2008-31
pp.13-18
ICD 2005-04-15
10:30
Fukuoka   A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture
Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy)
A 1Mbit MRAM with a 0.81um2 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) cell using 0.13um 4LM logic technology has... [more] ICD2005-13
pp.1-6
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