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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, CPSY, CAS | 2018-12-23 09:30 |
Okinawa | [Poster Presentation]
Design of VLIW processor for embedded applications based on RISC-V 16-bit ISA Yusuke Mitani, Shunya Makino, Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.)  CAS2018-93 ICD2018-77 CPSY2018-59 |
[more] | CAS2018-93 ICD2018-77 CPSY2018-59 p.69 |
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| ICD, CPSY, CAS | 2018-12-23 09:30 |
Okinawa | [Poster Presentation]
Development of a low-power processor based on RISC-V Shunya Makino, Yusuke Mitani, Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.) CAS2018-94 ICD2018-78 CPSY2018-60 |
[more] | CAS2018-94 ICD2018-78 CPSY2018-60 p.71 |
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| SDM, ICD, ITE-IST [detail] | 2018-08-07 16:45 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | Power Consumption Estimation by Die Temperature for Processors Implemented on FPGA Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.) SDM2018-35 ICD2018-22 |
The importance of thermal management and temperature sensing is increasing for processors with power consumption lower t... [more] | SDM2018-35 ICD2018-22 pp.53-58 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 16:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Integrated Machine Code Monitor on FPGA Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.) VLD2017-73 CPSY2017-117 RECONF2017-61 |
Machine code monitor is necessary for initial program development stage when implementing a new processor with unique IS... [more] | VLD2017-73 CPSY2017-117 RECONF2017-61 pp.65-70 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 13:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Optimal Design of FIR filter using a Real Coded Genetic Algorithm Processor Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) VLD2016-71 CPSY2016-107 RECONF2016-52 |
Evolutionary algorithms such as Genetic Algorithm (GA) are applied to the optimum design of digital filters. In generall... [more] | VLD2016-71 CPSY2016-107 RECONF2016-52 pp.7-12 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 14:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Proposal of Processor Enabling to Start-Up Internal Modules Distributed Energy Consumption Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.) VLD2016-87 CPSY2016-123 RECONF2016-68 |
Such sensor network applicatio, which is one of core technologies in IoT, are requesting a change for consuming energy o... [more] | VLD2016-87 CPSY2016-123 RECONF2016-68 pp.115-120 |
| COMP, IPSJ-AL | 2015-06-12 17:15 |
Hokkaido | A design of real coded genetic algorithm processor Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) COMP2015-8 |
In recent years, Real Coded Genetic Algorithm (RCGA) has been attracting attention. It is one of the GA for handling rea... [more] | COMP2015-8 pp.51-58 |
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| COMP, IPSJ-AL | 2015-06-12 17:40 |
Hokkaido | An FPGA Implementation of Correlation Processor Yuma Matsui, Akihiko Tsukahara, Akinori Kanasugi, Ki Ando (Tokyo Denki Univ.) COMP2015-9 |
Correlation calculation is the operation for obtaining the similarity of two sets of data. This operation is frequently ... [more] | COMP2015-9 pp.59-65 |
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| CPSY | 2008-12-18 15:40 |
Kyoto | KYOTO Research Park | A Reconfigurable Processor for Genetic Algorithm based on Redundant Binary Number Masanao Aoshima, Akinori Kanasugi (Tokyo Denki Univ.) CPSY2008-51 |
Genetic algorithm (GA) is one of solution search algorithms based on evolution of life. GA can avoid local minima becaus... [more] | CPSY2008-51 pp.49-54 |
| CPSY | 2008-12-18 16:10 |
Kyoto | KYOTO Research Park | An Architecture of Dynamically Reconfigurable Systolic Array and FPGA Implementation Toshiyuki Ishimura, Yuhki Hayakawa, Akinori Kanasugi (Tokyo Denki Univ.) CPSY2008-52 |
The dynamically reconfigurable processors which have high-speed performance of ASIC, flexibility of FPGA and high area e... [more] | CPSY2008-52 pp.55-60 |
| SIS | 2008-03-13 11:15 |
Tokyo | Musashi Institute of Technology(Setagaya) | An Architecture of Dynamically Reconfigurable Systolic Array Toshiyuki Ishimura, Akinori Kanasugi (TDU) SIS2007-70 |
The Dynamically Reconfigurable Device which has high-speed performance of ASIC, flexibility of FPGA and high area effici... [more] | SIS2007-70 pp.11-16 |
| ICD, ITE-CE | 2006-12-14 16:55 |
Hiroshima | A GA processor which can dynamically change number and accuracy of individuals Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) |
[more] | ICD2006-157 pp.79-84 |
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| SDM, VLD | 2006-09-26 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) |
This paper proposes a novel processor for genetic algorithm (GA) using dynamically reconfigurable memory. Ingeneral GA, ... [more] | VLD2006-39 SDM2006-160 pp.1-6 |
| ICD, ITE-CE | 2006-01-26 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Design of Rough Set Processor for Data Mining Mitsuhiro Matsumoto, Masao Ohkura, Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) |
[more] | ICD2005-210 pp.31-36 |
| NLP | 2005-12-16 15:10 |
Ibaraki | Ibaraki Univ. | A Circuit Design of Data-Mining Processor based on Rough Set Theory Masao Ohkura, Mitsuhiro Matsumoto, Akinori Kanasugi (Tokyo Denki univ.) |
[more] | NLP2005-93 pp.45-50 |
| ICD | 2004-12-16 16:45 |
Hiroshima | A design of architecture and circuit of data-mining processor Akinori Kanasugi, Masao Ohkura, Mitsuhiro Matsumoto (Tokyo Denki Univ.) |
This paper describes the architecture and circuit of rough set processor. The theory of rough sets has a lot of applicat... [more] | ICD2004-192 pp.55-58 |
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| IE, SIP, ICD, IPSJ-SLDM | 2004-10-22 16:15 |
Yamagata | Design of Cell Assignment Circuit for Dynamic Reconstruction Yutaka Koseki, Akinori Kanasugi (Tokyo Denki Univ.) |
[more] | SIP2004-102 ICD2004-134 IE2004-78 pp.79-84 |
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