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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 12 of 12  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, IPSJ-ARC 2013-02-01
11:40
Tokyo   Programming Circuit of Multi-level ReRAM Utilizing Voltage Sense-Amplifier
Taiki Ibe, Kazuya Nakayama, Akio Kitagawa (Kanazawa Univ.) ICD2012-126
For multi-level ReRAM memory, a novel read circuit using a VSA (Voltage Sense Amplifier) is proposed. This circuit compa... [more] ICD2012-126
pp.45-49
SDM, ICD 2011-08-25
14:55
Toyama Toyama kenminkaikan Novel power reduction technique for ReRAM with the automatic evasion circuit of the wasteful overwrite
Takaya Handa, Kazuya Nakayama, Akio Kitagawa, Junichi Akita (Kanazawa Univ.) SDM2011-80 ICD2011-48
ReRAM (Resistance Random Access Memory) is widely expected as a next generation memory and further researches have been ... [more] SDM2011-80 ICD2011-48
pp.53-57
ICD, ITE-IST 2011-07-21
11:45
Hiroshima Hiroshima Institute of Technology Design of Radical Sensor LSI with RF-CMOS Technology -- Sensitivity Analysis of the Detecting Circuit of ESR --
Shunsuke Kimura, Junichi Akita, Akio Kitagawa (Kanazawa Univ.) ICD2011-24
The detecting circuit of Electron Spin Resonance (ESR) for radical sensing and the detection sensitivity analysis of ESR... [more] ICD2011-24
pp.31-35
ICD, ITE-IST 2007-07-26
16:30
Hyogo   Component Circuits of Passive Sensor Tag for Biomedical Monitoring
Kouta Kano, Shingo Nakano, Junichi Akita, Akio Kitagawa (Kanazawa Univ) ICD2007-51
In this paper, we describe the component circuits of passive RF tag for biomedical monitoring using 950MHz-Band RF-tag s... [more] ICD2007-51
pp.83-88
ICD, ITE-IST 2007-07-27
11:35
Hyogo   A 426MHz transmitter for multiuser MIMO systems
Ryosei Makino, Shigeru Fujieda, Kei Hayase, Junichi Akita, Akio Kitagawa (Kanazawa Univ.) ICD2007-61
This paper describes mainly the design and simulation of transmitter complying with ARIB STD-T67 and RCR STD-30 standard... [more] ICD2007-61
pp.141-146
ICD 2006-04-14
08:40
Oita Oita University Nonvolatile SRAM based on Phase Change
Masashi Takata, Kazuya Nakayama, Takatomi Izumi, Toru Shinmura, Junichi Akita, Akio Kitagawa (Kanazawa Univ.)
 [more] ICD2006-10
pp.51-56
RECONF, CPSY, VLD, IPSJ-SLDM 2006-01-17
13:25
Kanagawa   Voice Recognition LSI based on FTTSS
Tomotaka Nakano, Park Hu Gang, Tetsuo Funada, Akio Kitagawa (Kanazawa Univ)
(Advance abstract in Japanese is available) [more] VLD2005-89 CPSY2005-45 RECONF2005-78
pp.7-12
RECONF, CPSY, VLD, IPSJ-SLDM 2006-01-17
15:50
Kanagawa   Multuiple Programming Method and Circuit Design for a Phase Change Nonvolatile Random Access Memory
Takatomi Izumi, Masashi Takata, Kazuya Nakayama, Akio Kitagawa (Kanazawa Univ.)
A novel multiple programming method for a phase change nonvolatile randamaccess memory(PRAM) is proposed. PRAM uses chal... [more] VLD2005-94 CPSY2005-50 RECONF2005-83
pp.37-42
AP, RCS
(Joint)
2005-10-21
13:25
Akita Akita Prefectural Univ. Wireless sensor network system using MIMO
Hisahiro Itou, Kei Hayase, Akio Kitagawa (Kanazawa Univ.)
This paper describes wireless sensor network using MIMO. The radio transmission channel multiplexed by MIMO is assigned ... [more] RCS2005-104
pp.115-120
CAS 2005-01-21
15:30
Ishikawa Kanazawa Univ High-Level Synthesis from Executable Code
Hidenori Ogata, Akio Kitagawa (Kanazawa Univ.)
In this work, we present a technique for automatically generating a synthesizable HDL code from an executable code. The ... [more] CAS2004-78
pp.35-40
CAS 2005-01-21
15:55
Ishikawa Kanazawa Univ Multiple Programming Method and Circuitry for PRAM
Masashi Takata, Kazuya Nakayama, Takatomi Izumi, Akio Kitagawa (Kanazawa Univ.)
A novel multiple programming method for a phase change nonvolatile random access memory (NVRAM) is proposed. The resista... [more] CAS2004-79
pp.41-46
CAS 2005-01-21
16:20
Ishikawa Kanazawa Univ Nonvolatile SRAM based on Phase Change
Masashi Takata, Kazuya Nakayama, Takatomi Izumi, Toru Shinmura, Akio Kitagawa (Kanazawa Univ.)
We propose a novel architecture combining SRAM with PRAM (Phase Change nonvolatile RAM). This architecture (termed PNSRA... [more] CAS2004-80
pp.47-52
 Results 1 - 12 of 12  /   
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