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All Technical Committee Conferences  (Searched in: Recent 10 Years)

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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 17 of 17  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, RECONF 2025-01-17
14:45
Kanagawa Yokohama Technology Campus Flagship Building (Kanagawa, Online)
(Primary: On-site, Secondary: Online)
Development of Self-Calibration Hardware Interface for a Peripheral on Super General Purpose SoC
Hibiki Shinozaki, Akira Yamawaki (KIT) VLD2024-97 RECONF2024-127
Super general purpose SoC (System on chip) has dedicated hardware interfaces for all peripherals and dynamically reconfi... [more] VLD2024-97 RECONF2024-127
pp.116-121
SIS, ITE-BCT 2024-10-04
11:00
Hokkaido Hokusei Gakuen Univ. (Hokkaido, Online)
(Primary: On-site, Secondary: Online)
Development of single frame sprite drawing hardware in High-level Synthesis
Yuka Otani, Akira Yamawaki (Kyutech) SIS2024-25
As part of a hardware-oriented game library created using high-level synthesis, the development of hardware capable of d... [more] SIS2024-25
pp.47-52
VLD, CAS, SIP, MSS 2024-07-19
14:15
Aomori (Aomori, Online)
(Primary: On-site, Secondary: Online)
Operable Time Evaluation of FPGA-based Sensor Node with Capacitor Power Supply Varying Basic Circuit Resources
Itsuki Fukumitsu, Akira Yamawaki (Kyutech) CAS2024-22 VLD2024-22 SIP2024-39 MSS2024-22
We propose a low-power and maintenance-free wireless-wired hierarchical sensor network using zero standby power sensor n... [more] CAS2024-22 VLD2024-22 SIP2024-39 MSS2024-22
pp.117-121
SIS 2024-06-06
15:20
Hiroshima Hiroshima University (Hiroshima, Online)
(Primary: On-site, Secondary: Online)
Development of sprite drawing hardware combining high-level synthesis and FPGA internal memory
Keigo Aoki, Akira Yamawaki (Kyutech) SIS2024-6
Mobile terminals are required to have higher performance and functionality while conserving even more power. To realize ... [more] SIS2024-6
pp.29-34
SIS 2024-06-06
16:30
Hiroshima Hiroshima University (Hiroshima, Online)
(Primary: On-site, Secondary: Online)
Hardware Implementation of Calibration Data Loading Part in Device Driver for an SPI Peripheral
Hibiki Shinozaki, Akira Yamawaki (Kyutech) SIS2024-9
Device drivers that control SPI devices will not be able to maximize their performance due to software overhead. In this... [more] SIS2024-9
pp.45-49
ICTSSL, CAS 2024-01-25
11:00
Kanagawa (Kanagawa, Online)
(Primary: On-site, Secondary: Online)
Performance effect of memory access pattern for high-level synthesized sprite drawing hardware
Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-85 ICTSSL2023-38
We are developing a sprite drawing hardware suitable for high-level synthesis. Sprite drawing stores the sprite image in... [more] CAS2023-85 ICTSSL2023-38
pp.17-22
SIS 2023-12-07
11:00
Aichi Sakurayama Campus, Nagoya City University (Aichi, Online)
(Primary: On-site, Secondary: Online)
Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware
Yuka Otani, Akira Yamawaki (Kyutech) SIS2023-24
A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve h... [more] SIS2023-24
pp.1-6
SIS 2023-12-07
11:20
Aichi Sakurayama Campus, Nagoya City University (Aichi, Online)
(Primary: On-site, Secondary: Online)
Development of a real-time non-photorealistic rendering system with a high-level synthesized pencil drawing style image conversion hardware
Honoka Tani, Akira Yamawaki (Kyutech) SIS2023-25
We developed non-photorealistic rendering (NPR) libraries optimized for high-level synthesis (HLS) technology that autom... [more] SIS2023-25
pp.7-12
MSS, CAS, SIP, VLD 2023-07-06
09:30
Hokkaido (Hokkaido, Online)
(Primary: On-site, Secondary: Online)
Performance Improvement by Integrating Former and Latter Processes of Pencil Drawing Style Image Conversion on High-Level Synthesized Hardware.
Honoka Tani, Akira Yamawaki (Kyutech) CAS2023-1 VLD2023-1 SIP2023-17 MSS2023-1
We are developing hardware to realize a high-performance and low-power embedded image processing device using high-level... [more] CAS2023-1 VLD2023-1 SIP2023-17 MSS2023-1
pp.1-5
MSS, CAS, SIP, VLD 2023-07-06
10:10
Hokkaido (Hokkaido, Online)
(Primary: On-site, Secondary: Online)
Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware
Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3
A mobile terminal with hardware reconfigurability can achieve higher performance and lower power consumption by performi... [more] CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3
pp.10-15
CAS, CS 2023-03-01
14:50
Fukuoka Kitakyushu International Conference Center (Fukuoka, Online)
(Primary: On-site, Secondary: Online)
Memory access optimization for former process of pencil drawing style image conversion in High-level Synthesis
Honoka Tani, Akira Yamawaki (Kyutech) CAS2022-105 CS2022-82
To effectively use high-level synthesis, which automatically converts software to hardware, it is necessary to create so... [more] CAS2022-105 CS2022-82
pp.53-58
CAS, MSS, IPSJ-AL [detail] 2022-11-18
16:00
Kochi (Kochi, Online)
(Primary: On-site, Secondary: Online)
An Investigation of Software Describing Methods to Design Parallax Background Scrolling Hardware in High-level Synthesis
Kilryong Lee, Akira Yamawaki (KIT) CAS2022-59 MSS2022-42
We are developing a game programing library which can be converted to hardware modules by High-Level Synthesis, HLS tech... [more] CAS2022-59 MSS2022-42
pp.105-110
IE, ITS, ITE-AIT, ITE-ME, ITE-MMS [detail] 2022-02-22
14:25
Online Online (Online) Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction
Kohei Shinyamada, Akira Yamawaki (Kyutech) ITS2021-61 IE2021-70
In this study, we developed a median-based dynamic background subtraction image processing system equipped with a real c... [more] ITS2021-61 IE2021-70
pp.214-218
ICTSSL, CAS 2020-01-30
18:00
Tokyo   (Tokyo) High-level synthesis oriented histogram series duplication for overlapping continuous image processing
Moena Yamasaki, Akira Yamawaki (Kyutech) CAS2019-80 ICTSSL2019-49
In order to quickly realize a high-performance and power-saving embedded image processing device, it is effective to use... [more] CAS2019-80 ICTSSL2019-49
pp.85-89
IT 2018-09-05
09:45
Iwate Seionsou (Iwate) An Upper Bound on the Generalized Cayley Distance
Akira Yamawaki, Hiroshi Kamabe, Shan Lu (Gifu Univ.) IT2018-28
Generalized Cayley distance is one of distances which are considered in permutation codes. The generalized Cayley distan... [more] IT2018-28
pp.7-12
EMM, IT 2017-05-23
14:00
Yamagata Yamagata University(Yonezawa Campus) (Yamagata) Construction of Parallel RIO Codes using Coset Coding with Hamming Codes
Akira Yamawaki, Hiroshi Kamabe, Shan Lu (Gifu Univ.) IT2017-13 EMM2017-13
Random I/O (RIO) code is a coding scheme that enables to read one logical page using a single read threshold in multilev... [more] IT2017-13 EMM2017-13
pp.73-78
IT 2015-07-14
11:20
Tokyo Tokyo Institute of Technology (Tokyo) Maximization of Number of Rewritings for Index-less Indexed Flash Codes with Bits for Reversal
Akira Yamawaki (Gifu Univ.), Hironori Uchikawa (Toshiba), Hiroshi Kamabe (Gifu Univ.) IT2015-32
The index-less indexed flash code(ILIFC) with bits for reversal is a variant of a coding scheme proposed by Mahdavifar e... [more] IT2015-32
pp.89-94
 Results 1 - 17 of 17  /   
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