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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 93  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
10:20
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
A fast SRAF optimization used LUT based intensity estimation
Sota Saito, Atsushi Takahashi (Tokyo Tech)
 [more]
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
10:45
Ishikawa Kanazawa Bunka Hall
(Primary: On-site, Secondary: Online)
Mask Optimization Using Voronoi Partition and Iterative Improvement
Naoki Nonaka, Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA)
 [more]
VLD, HWS [detail] 2022-03-07
09:35
Online Online Bottleneck Channel Routing to Reduce the Area of Analog VLSI
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat) VLD2021-77 HWS2021-54
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2021-77 HWS2021-54
pp.7-12
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2021-12-02
15:35
Online Online Mask Optimization Method Using Simulated Quantum Annealing
Yukihide Kohira, Haruki Nakayama, Naoki Nonaka (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA Corporation) VLD2021-45 ICD2021-55 DC2021-51 RECONF2021-53
To realize continuously scaling down of technology node, progressing manufacturing process by optical lithography is req... [more] VLD2021-45 ICD2021-55 DC2021-51 RECONF2021-53
pp.162-167
BioX, CNR 2020-03-04
17:10
Tokyo
(Cancelled but technical report was issued)
Pre-classifier Using Finger Pressure and Touch Area on Tablet in Person Verification Based on Finger-Writing of Simple Symbol
Yohei Masegi, Atsushi Takahashi, Isao Nakanishi (Tottori Univ.) BioX2019-66 CNR2019-49
 [more] BioX2019-66 CNR2019-49
pp.25-30
HWS, VLD [detail] 2020-03-04
09:55
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
A Pin-Pair Routing Method for Length Difference Reduction in Set-Pair Routing
Kunihiko Wada, Shimpei Sato, Atsushi Takahashi (TokyoTech) VLD2019-95 HWS2019-68
In this paper, we propose a Routing method that aims to reduce total wire length and wire length difference for Set-Pair... [more] VLD2019-95 HWS2019-68
pp.7-12
HWS, VLD [detail] 2020-03-04
16:00
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
Pixel-based Mask Optimization with Lagrangian Relaxation and Boundary Flipping
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2019-105 HWS2019-78
Due to miniaturization of process technology, progressing manufacturing process by optical lithography is required. In r... [more] VLD2019-105 HWS2019-78
pp.65-70
HWS, VLD [detail] 2020-03-04
16:25
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
Machine Learning Based Lithography Hotspot Detection Method and Evaluation
Hidekazu Takahashi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2019-106 HWS2019-79
As VLSI device feature sizes are getting smaller and smaller, layout design
has become more important to keep the yield... [more]
VLD2019-106 HWS2019-79
pp.71-76
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
16:10
Ehime Ehime Prefecture Gender Equality Center Analysis of databases used for hot spot test cases
Hiroki Ogura, Hidekazu Takahashi, Sinpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2019-52 DC2019-76
With the miniaturization of semiconductor circuit patterns, the importance of photolithography has increased. In the sta... [more] VLD2019-52 DC2019-76
pp.191-196
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
16:35
Ehime Ehime Prefecture Gender Equality Center Mask Optimization Considering Process Variation by Subgradient Method
Yukihide Kohira, Rina Azuma (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2019-53 DC2019-77
Due to miniaturization of process technology, progressing manufacturing process by optical lithography is required. In r... [more] VLD2019-53 DC2019-77
pp.197-202
HWS, VLD 2019-02-27
13:55
Okinawa Okinawa Ken Seinen Kaikan Set-Pair Routing Algorithm with Selective Pin-Pair Connections
Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2018-99 HWS2018-62
We propose a set-pair routing algorithm which efficiently generates a length matched routing pattern. In our algorithm, ... [more] VLD2018-99 HWS2018-62
pp.37-42
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-30
10:30
Kanagawa Raiosha, Hiyoshi Campus, Keio University On Delay Optimization for Improving General Synchronous Performance
Eijiro Sassa, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2018-72 CPSY2018-82 RECONF2018-46
 [more] VLD2018-72 CPSY2018-82 RECONF2018-46
pp.1-6
NC, MBE
(Joint)
2018-12-15
15:30
Aichi Nagoya Institute of Technology Proposal of Analysis Accuracy Improvement Method by Logistic Regression in Single Nucleotide Polymorphism Analysis Using Next-Generation Sequencer
Ginji Azuma (Kindai Univ.), Atsushi Takahashi (NCVC), Naoki Ohboshi (Kindai Univ.) NC2018-37
Single nucleotide polymorphisms are known to be related to phenotypes, and analysis is actively performed. However, the ... [more] NC2018-37
pp.51-55
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
14:10
Hiroshima Satellite Campus Hiroshima Process Variation-aware Model-based OPC using 0-1 Quadratic Programming
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC) VLD2018-70 DC2018-56
Due to continuous shrinking of Critical Dimensions (CD) of layout pattern in VLSI, advances of manufacturing process in ... [more] VLD2018-70 DC2018-56
pp.209-214
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-08
15:30
Kumamoto Kumamoto-Kenminkouryukan Parea A Study on Target Pin-Pairs Selection for Set-Pair Routing
Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech.) VLD2017-59 DC2017-65
 [more] VLD2017-59 DC2017-65
pp.235-240
SIP, CAS, MSS, VLD 2017-06-20
15:30
Niigata Niigata University, Ikarashi Campus Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit
Yuta Ukon, Shimpei Sato, Atsushi Takahashi (Tokyo Inst. of Tech.) CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23
There are a lot of high load processing that is not required high accuracy at the data center. An approximate computing ... [more] CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23
pp.119-124
VLD, IPSJ-SLDM 2017-05-10
16:05
Fukuoka Kitakyushu International Conference Center [Invited Talk] Launch of IEEE CEDA All Japan Joint Chapter and Its Role
Atsushi Takahashi (Tokyo Tech) VLD2017-3
IEEE the Council on Electronic Design Automation (CEDA) All Japan Joint Chapter (AJJC) was founded in 2014. In this manu... [more] VLD2017-3
pp.13-16
VLD 2017-03-02
10:30
Okinawa Okinawa Seinen Kaikan High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering
Shohei Handa, Shimpei Sato, Atsushi Takahashi (Tokyo TECH) VLD2016-111
 [more] VLD2016-111
pp.55-60
VLD 2017-03-02
11:20
Okinawa Okinawa Seinen Kaikan Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning
Atsushi Ogashira, Shimpei Sato, Atsushi Takahashi (Tokyo TECH) VLD2016-113
In current semiconductor design, high quality and short time design is required.
In an advanced lithography technology... [more]
VLD2016-113
pp.67-72
VLD 2017-03-02
11:45
Okinawa Okinawa Seinen Kaikan Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing
Shun Sugihara, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2016-114
In printed circuit board, to meet requirements such as delay and noise,
routing of each net is necessary to achieve its... [more]
VLD2016-114
pp.73-78
 Results 1 - 20 of 93  /  [Next]  
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