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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 100  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS, ICD 2024-02-28
15:30
Okinawa
(Primary: On-site, Secondary: Online)
A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem
Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (JEDAT) VLD2023-102 HWS2023-62 ICD2023-91
 [more] VLD2023-102 HWS2023-62 ICD2023-91
pp.18-23
VLD, HWS, ICD 2024-02-28
15:55
Okinawa
(Primary: On-site, Secondary: Online)
Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (Jedat) VLD2023-103 HWS2023-63 ICD2023-92
 [more] VLD2023-103 HWS2023-63 ICD2023-92
pp.24-29
VLD, HWS, ICD 2024-02-28
16:20
Okinawa
(Primary: On-site, Secondary: Online)
Single Trunk Routing Problem for Generalized Channel
Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi (Tokyo Tech) VLD2023-104 HWS2023-64 ICD2023-93
This paper addresses the challenges posed by tight horizontal routing capacity in critical layers of chip design. A Gene... [more] VLD2023-104 HWS2023-64 ICD2023-93
pp.30-35
HWS, VLD 2023-03-01
14:55
Okinawa
(Primary: On-site, Secondary: Online)
High fidelity mask pattern generation method by amplitude component evaluation
Yu Horimoto, Sota Saito, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA) VLD2022-79 HWS2022-50
 [more] VLD2022-79 HWS2022-50
pp.37-42
HWS, VLD 2023-03-01
15:20
Okinawa
(Primary: On-site, Secondary: Online)
A fast SRAF optimization using Voronoi diagram and LUT based intensity evaluation
Sota Saito, Yu Horimoto, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA) VLD2022-80 HWS2022-51
Recent advances in technology nodes have led to problems in optical lithography such as reduced fidelity of transferred ... [more] VLD2022-80 HWS2022-51
pp.43-48
HWS, VLD 2023-03-03
09:55
Okinawa
(Primary: On-site, Secondary: Online)
Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat) VLD2022-101 HWS2022-72
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2022-101 HWS2022-72
pp.149-154
HWS, VLD 2023-03-03
10:20
Okinawa
(Primary: On-site, Secondary: Online)
Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints
Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (JEDAT) VLD2022-102 HWS2022-73
In analog integrated circuits, designs usually rely on the relative accuracy of device characteristics. The purpose of t... [more] VLD2022-102 HWS2022-73
pp.155-160
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
10:20
Kumamoto  
(Primary: On-site, Secondary: Online)
A fast SRAF optimization used LUT based point intensity calculation
Sota Saito, Atsushi Takahashi (Tokyo Tech) VLD2022-40 ICD2022-57 DC2022-56 RECONF2022-63
Recent advances in technology nodes have led to problems in optical lithography such as reduced fidelity of transferred ... [more] VLD2022-40 ICD2022-57 DC2022-56 RECONF2022-63
pp.121-126
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
10:45
Kumamoto  
(Primary: On-site, Secondary: Online)
Mask Optimization Using Voronoi Partition and Iterative Improvement
Naoki Nonaka, Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2022-41 ICD2022-58 DC2022-57 RECONF2022-64
To realize continuously scaling down technology node, progressing manufacturing process by optical lithography is requir... [more] VLD2022-41 ICD2022-58 DC2022-57 RECONF2022-64
pp.127-132
VLD, HWS [detail] 2022-03-07
09:35
Online Online Bottleneck Channel Routing to Reduce the Area of Analog VLSI
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat) VLD2021-77 HWS2021-54
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2021-77 HWS2021-54
pp.7-12
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2021-12-02
15:35
Online Online Mask Optimization Method Using Simulated Quantum Annealing
Yukihide Kohira, Haruki Nakayama, Naoki Nonaka (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA Corporation) VLD2021-45 ICD2021-55 DC2021-51 RECONF2021-53
To realize continuously scaling down of technology node, progressing manufacturing process by optical lithography is req... [more] VLD2021-45 ICD2021-55 DC2021-51 RECONF2021-53
pp.162-167
BioX, CNR 2020-03-04
17:10
Tokyo
(Cancelled but technical report was issued)
Pre-classifier Using Finger Pressure and Touch Area on Tablet in Person Verification Based on Finger-Writing of Simple Symbol
Yohei Masegi, Atsushi Takahashi, Isao Nakanishi (Tottori Univ.) BioX2019-66 CNR2019-49
 [more] BioX2019-66 CNR2019-49
pp.25-30
HWS, VLD [detail] 2020-03-04
09:55
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
A Pin-Pair Routing Method for Length Difference Reduction in Set-Pair Routing
Kunihiko Wada, Shimpei Sato, Atsushi Takahashi (TokyoTech) VLD2019-95 HWS2019-68
In this paper, we propose a Routing method that aims to reduce total wire length and wire length difference for Set-Pair... [more] VLD2019-95 HWS2019-68
pp.7-12
HWS, VLD [detail] 2020-03-04
16:00
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
Pixel-based Mask Optimization with Lagrangian Relaxation and Boundary Flipping
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2019-105 HWS2019-78
Due to miniaturization of process technology, progressing manufacturing process by optical lithography is required. In r... [more] VLD2019-105 HWS2019-78
pp.65-70
HWS, VLD [detail] 2020-03-04
16:25
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
Machine Learning Based Lithography Hotspot Detection Method and Evaluation
Hidekazu Takahashi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2019-106 HWS2019-79
As VLSI device feature sizes are getting smaller and smaller, layout design
has become more important to keep the yield... [more]
VLD2019-106 HWS2019-79
pp.71-76
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
16:10
Ehime Ehime Prefecture Gender Equality Center Analysis of databases used for hot spot test cases
Hiroki Ogura, Hidekazu Takahashi, Sinpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2019-52 DC2019-76
With the miniaturization of semiconductor circuit patterns, the importance of photolithography has increased. In the sta... [more] VLD2019-52 DC2019-76
pp.191-196
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
16:35
Ehime Ehime Prefecture Gender Equality Center Mask Optimization Considering Process Variation by Subgradient Method
Yukihide Kohira, Rina Azuma (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2019-53 DC2019-77
Due to miniaturization of process technology, progressing manufacturing process by optical lithography is required. In r... [more] VLD2019-53 DC2019-77
pp.197-202
HWS, VLD 2019-02-27
13:55
Okinawa Okinawa Ken Seinen Kaikan Set-Pair Routing Algorithm with Selective Pin-Pair Connections
Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2018-99 HWS2018-62
We propose a set-pair routing algorithm which efficiently generates a length matched routing pattern. In our algorithm, ... [more] VLD2018-99 HWS2018-62
pp.37-42
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-30
10:30
Kanagawa Raiosha, Hiyoshi Campus, Keio University On Delay Optimization for Improving General Synchronous Performance
Eijiro Sassa, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2018-72 CPSY2018-82 RECONF2018-46
 [more] VLD2018-72 CPSY2018-82 RECONF2018-46
pp.1-6
NC, MBE
(Joint)
2018-12-15
15:30
Aichi Nagoya Institute of Technology Proposal of Analysis Accuracy Improvement Method by Logistic Regression in Single Nucleotide Polymorphism Analysis Using Next-Generation Sequencer
Ginji Azuma (Kindai Univ.), Atsushi Takahashi (NCVC), Naoki Ohboshi (Kindai Univ.) NC2018-37
Single nucleotide polymorphisms are known to be related to phenotypes, and analysis is actively performed. However, the ... [more] NC2018-37
pp.51-55
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