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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2022-03-01
13:45
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
A Logic Locking Method based on SFLL-hd at Register Transfer Level
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] DC2021-72
pp.45-50
DC 2021-12-10
14:00
Kagawa
(Primary: On-site, Secondary: Online)
A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2021-57
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design co... [more] DC2021-57
pp.13-18
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
12:00
Online Online A Logic Locking Method Based on Anti-SAT at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-64 DC2020-94
In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design... [more] CPSY2020-64 DC2020-94
pp.85-90
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
17:30
Online Online An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-15 DC2020-15
In recent year, controller augmentation has been used for design-for-testability and design-for-security at register tra... [more] CPSY2020-15 DC2020-15
pp.93-98
 Results 1 - 4 of 4  /   
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