Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, VLD |
2023-03-01 14:55 |
Okinawa |
(Primary: On-site, Secondary: Online) |
High fidelity mask pattern generation method by amplitude component evaluation Yu Horimoto, Sota Saito, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA) VLD2022-79 HWS2022-50 |
[more] |
VLD2022-79 HWS2022-50 pp.37-42 |
HWS, VLD |
2023-03-01 15:20 |
Okinawa |
(Primary: On-site, Secondary: Online) |
A fast SRAF optimization using Voronoi diagram and LUT based intensity evaluation Sota Saito, Yu Horimoto, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA) VLD2022-80 HWS2022-51 |
Recent advances in technology nodes have led to problems in optical lithography such as reduced fidelity of transferred ... [more] |
VLD2022-80 HWS2022-51 pp.43-48 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-30 10:45 |
Kumamoto |
(Primary: On-site, Secondary: Online) |
Mask Optimization Using Voronoi Partition and Iterative Improvement Naoki Nonaka, Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2022-41 ICD2022-58 DC2022-57 RECONF2022-64 |
To realize continuously scaling down technology node, progressing manufacturing process by optical lithography is requir... [more] |
VLD2022-41 ICD2022-58 DC2022-57 RECONF2022-64 pp.127-132 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 15:35 |
Online |
Online |
Mask Optimization Method Using Simulated Quantum Annealing Yukihide Kohira, Haruki Nakayama, Naoki Nonaka (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA Corporation) VLD2021-45 ICD2021-55 DC2021-51 RECONF2021-53 |
To realize continuously scaling down of technology node, progressing manufacturing process by optical lithography is req... [more] |
VLD2021-45 ICD2021-55 DC2021-51 RECONF2021-53 pp.162-167 |
HWS, VLD [detail] |
2020-03-04 16:00 |
Okinawa |
Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Pixel-based Mask Optimization with Lagrangian Relaxation and Boundary Flipping Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2019-105 HWS2019-78 |
Due to miniaturization of process technology, progressing manufacturing process by optical lithography is required. In r... [more] |
VLD2019-105 HWS2019-78 pp.65-70 |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-15 16:35 |
Ehime |
Ehime Prefecture Gender Equality Center |
Mask Optimization Considering Process Variation by Subgradient Method Yukihide Kohira, Rina Azuma (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2019-53 DC2019-77 |
Due to miniaturization of process technology, progressing manufacturing process by optical lithography is required. In r... [more] |
VLD2019-53 DC2019-77 pp.197-202 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-07 14:10 |
Hiroshima |
Satellite Campus Hiroshima |
Process Variation-aware Model-based OPC using 0-1 Quadratic Programming Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC) VLD2018-70 DC2018-56 |
Due to continuous shrinking of Critical Dimensions (CD) of layout pattern in VLSI, advances of manufacturing process in ... [more] |
VLD2018-70 DC2018-56 pp.209-214 |
VLD, IPSJ-SLDM |
2014-05-29 11:30 |
Fukuoka |
Kitakyushu International Conference Center |
LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) VLD2014-6 |
One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently... [more] |
VLD2014-6 pp.27-32 |
VLD |
2014-03-04 13:20 |
Okinawa |
Okinawa Seinen Kaikan |
[Invited Talk]
Advanced Model-Based Hotspot Fix Flow for Layout Optimization with Genetic Algorithm Shuhei Sota (Toshiba Microelectronics), Taiga Uno, Masanari Kajiwara, Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Ryota Aburada, Toshiya Kotani (Toshiba), Kei Nakagawa, Tamaki Saito (Toshiba Microelectronics) VLD2013-148 |
Under the low-k1 lithography process, many hotspots are generated and their reduction is an urgent issue for mass produc... [more] |
VLD2013-148 p.85 |
VLD |
2014-03-04 14:15 |
Okinawa |
Okinawa Seinen Kaikan |
Self-Aligned Double Patterning-Aware Modified Two-color Grid Routing Takeshi Ihara, Atsushi Takahashi (Tokyo Inst. of Tech.), Chikaaki Kodama (TOSHIBA) VLD2013-150 |
[more] |
VLD2013-150 pp.93-98 |
VLD |
2014-03-04 14:40 |
Okinawa |
Okinawa Seinen Kaikan |
Self-Aligned Double and Quadruple Patterning-Aware Grid Routing Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Fumiharu Nakajima, Koichi Nakayama, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-151 |
Self-Aligned Double and Quadruple Patterning (SADP, SAQP) are leading candidates for sub-$20~nm$ and sub-$14~nm$ node an... [more] |
VLD2013-151 pp.99-104 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 13:00 |
Miyazaki |
NewWelCity Miyazaki |
Layout Methodology for Self-Alinged Double Patterning Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto (Toshiba) VLD2011-76 DC2011-52 |
We propose a new layout method for the damascene process of
self-aligned double patterning (SADP).
In this method, w... [more] |
VLD2011-76 DC2011-52 pp.141-146 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-22 13:00 |
Fukuoka |
Kitakyushu International Conference Center |
Necessary and Sufficient Conditions for Symmetry Placements Kunihiro Fujiyoshi, Chikaaki Kodama, Shinichi Koda (TUAT) |
(To be available after the conference date) [more] |
VLD2007-95 DC2007-50 pp.37-41 |
VLD, ICD, DC, IPSJ-SLDM |
2005-12-01 17:05 |
Fukuoka |
Kitakyushu International Conference Center |
Floorplan Design for 3D-VLSI Hidenori Ohta (Tokyo Univ. of Agri. & Tech.), Toshinori Yamada (Saitama Univ.), Chikaaki Kodama, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. & Tech.) |
[more] |
VLD2005-75 ICD2005-170 DC2005-52 pp.85-90 |