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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD |
2024-04-11 13:25 |
Kanagawa |
(Primary: On-site, Secondary: Online) |
[Invited Lecture]
Demonstration of Accelerated STT-Switching and High Retention in a scaled MTJ towards High-Density STT-MRAM Shogo Itai, Masaru Toko, Hideyuki Sugiyama, Chikayoshi Kamata, Rina Takashima, Takeo Koike, Masahiko Nakayama (Kioxia Corporation) ICD2024-5 |
[more] |
ICD2024-5 p.17 |
SDM |
2016-01-28 15:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126 |
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] |
SDM2015-126 pp.27-30 |
ICD |
2015-04-17 12:40 |
Nagano |
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[Invited Talk]
Low-power Embedded Perpendicular STT-MRAM Design for Cache Memory Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Chika Tanaka, Chikayoshi Kamata, Minoru Amano, Eiji Kitagawa, Naoharu Shimomura, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) ICD2015-10 |
[more] |
ICD2015-10 pp.45-50 |
SDM |
2015-01-27 14:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2014-142 |
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] |
SDM2014-142 pp.29-32 |
MRIS, ITE-MMS |
2014-10-03 09:30 |
Niigata |
Kashiwazaki energy hall, Niigata |
* Daisuke Saida, Naoharu Shimomura, Eiji Kitagawa, Chikayoshi Kamata, Megumi Yakabe, Yuuichi Osawa, Shinobu Fujita, Junichi Ito (Toshiba) MR2014-18 |
(To be available after the conference date) [more] |
MR2014-18 pp.27-31 |
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